Memory Controller Multi-Buffer Segmentation for Rapid Program Suspension
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Solution Overview
Problem
Existing memory systems face challenges in rapidly and stably suspending or stopping program operations when suddenly interrupted, particularly in handling multi-level cell memory devices, which affects data input/output efficiency and reliability.
Innovation Solution
A memory system comprising multiple memory devices with M-bit multi-level cells, multi-buffers, and transmission buffers, along with a controller that manages data caching and programming, performs necessary and secondary preparation operations to ensure efficient data sorting, checking, and voltage generation, allowing for rapid suspension or stopping of program operations without completing the program preparation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system performs complete program preparation operations including data sorting, checking, and voltage generation before programming, then the programming reliability is improved, but the time required to suspend or stop program operations increases when interruption is needed
Solution Approach 1:
The program preparation operation is divided into two distinct phases: a first preparation operation (data sorting) that can be interrupted, and a second preparation operation (data checking and voltage generation) that should not be interrupted. This segmentation allows the system to perform necessary preparation while enabling safe suspension points, resolving the contradiction between reliability and suspension time.
Solution Approach 2:
The data sorting operation is performed as a preliminary action before data checking and voltage generation. By completing the sorting phase first, the system prepares data in advance in a state that allows for safe interruption, while still maintaining the ability to complete the remaining preparation operations if needed. This preliminary action reduces the time penalty for suspension.
2Productivity
If the memory system uses M-bit multi-buffers to store program data before programming, then the data input efficiency is improved, but the complexity of managing buffer operations increases
Solution Approach 1:
The M-bit multi-buffers serve multiple functions: they store program data during input, maintain data in a suspended state when program operations are interrupted, and facilitate data transfer to memory cells. This multi-functionality improves data input efficiency while avoiding the need for separate buffering mechanisms, thereby managing complexity.
Solution Approach 2:
The multi-buffers act as an intermediary between the data input interface and the programming operation. They decouple the data input process from the programming execution, allowing efficient data loading while providing a controlled interface for suspension and resumption of operations, thus managing the complexity of buffer operations.
3Loss of time
If the controller performs data sorting operation before data checking and voltage generation, then the program preparation time is reduced for interrupted operations, but the data integrity verification must be delayed
Solution Approach 1:
The program preparation operation is segmented into distinct phases: data sorting (first preparation operation) and data checking with voltage generation (second preparation operation). This segmentation allows the system to complete sorting quickly for potential suspension, while preserving the ability to perform integrity verification later, thus balancing preparation time with reliability.
Solution Approach 2:
The system dynamically adapts the program preparation process based on whether suspension is required. If suspension occurs after sorting, the system can resume and complete the checking phase. This dynamic approach optimizes preparation time for interrupted operations while ensuring data integrity verification is ultimately performed, resolving the contradiction between speed and reliability.
Data Source
AI summary
A memory system may include a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.