Multi-Level CRC in Memory Controllers for Internal Data Integrity
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Solution Overview
Problem
Flash memory systems face inefficiencies in data updates due to the need to erase and rewrite entire blocks, leading to higher frequency of erase cycles and limited endurance, which is undesirable given the limited endurance of flash memory devices.
Innovation Solution
A non-volatile memory system with a controller circuit that generates and checks redundancy codes for data integrity during transfer, allowing for error detection and correction, and optimizing interface settings based on feedback mechanisms to improve performance and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data updates are performed by erasing and rewriting entire blocks, then data can be written to flash memory, but the frequency of erase cycles increases and endurance is reduced
Solution Approach 1:
The patent divides the flash memory block into multiple pages, allowing data to be updated at the page level rather than requiring erasure of the entire block. This segmentation enables partial updates, reducing the frequency of full block erase cycles and thereby improving endurance while maintaining data update capability.
2Reliability
If redundancy codes are generated and checked for every data transfer, then data integrity is improved, but processing time and complexity increase
Solution Approach 1:
The patent generates redundancy codes in advance during the data writing process, before the actual data transfer is complete. This preliminary generation of error correction codes allows for efficient error detection and correction without requiring complex real-time processing during data retrieval, thus improving data integrity while managing processing complexity.
3Productivity
If interface settings are optimized based on feedback, then performance is improved, but system complexity and processing overhead increase
Solution Approach 1:
The patent implements a feedback mechanism that monitors data transfer performance and error rates, then automatically adjusts interface settings such as transfer speed and error correction levels. This dynamic optimization improves interface performance by adapting to actual operating conditions while the automated nature of the feedback loop minimizes the complexity overhead.
Data Source
AI summary
In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set.