Memory Controller Decoding for Multi-Bit Non-Volatile Memory Errors
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Solution Overview
Problem
Existing memory systems face challenges in efficiently correcting errors in non-volatile memory, particularly when the number of error bits exceeds one, leading to decoding failures and reduced data integrity.
Innovation Solution
A memory controller employs a decoding method that calculates syndromes from received words, estimates the number of error bits, and performs variable transformation on an error locator polynomial to correct errors of up to three bits using a simplified configuration by utilizing specific polynomial transformations and inverse operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used, then decoding can be performed, but error correction capability is insufficient when error bits exceed one
Solution Approach 1:
The decoding process is segmented into distinct stages: syndrome calculation, error bit estimation, conditional variable transformation, and root calculation. This segmentation allows the system to handle different error scenarios (1-bit vs. 2-3 bit errors) through separate processing paths, improving error correction capability while managing complexity through structured organization of decoding operations
Solution Approach 2:
The patent applies parameter changes by transforming the error locator polynomial through variable substitution (changing the mathematical parameter representation) when 2-3 bit errors are detected. This parameter transformation enables the decoding system to adapt its calculation approach based on the error condition, enhancing reliability for multi-bit errors while maintaining efficient processing through conditional logic
2Reliability
If error correction is performed for multiple error bits, then data integrity improves, but decoding complexity increases
Solution Approach 1:
The decoding system dynamically adjusts its processing complexity based on the detected error condition. When syndrome calculation indicates 1-bit errors, the system follows a simpler path; when 2-3 bit errors are detected, it activates the variable transformation and root calculation procedures. This dynamic adaptation ensures data integrity for multiple error types while optimizing resource usage by applying complex operations only when necessary
Solution Approach 2:
The syndrome calculation results provide feedback that determines the subsequent decoding path. Based on the syndrome values, the system estimates the number of error bits and selects the appropriate correction methodology. This feedback mechanism enables the system to maintain high data integrity by accurately identifying error conditions while managing complexity through conditional processing based on real-time syndrome analysis
Data Source
AI summary
A memory system includes a non-volatile memory and a memory controller. The memory stores data encoded with an error correction code for correcting errors of n (n is 3 or more) bits or less. The controller estimates the number of error bits by using syndromes calculated from a received word. When the number of error bits is two or three, the controller executes variable transformation on a variable of an error locator polynomial corresponding to the number of error bits with a first value or a second value based on the syndromes. The controller also executes, with the first/second values, calculation of roots of a transformed polynomial obtained by converting the error locator polynomial. The controller obtains roots of the error locator polynomial by variable inverse transformation on the roots of the transformed polynomial and corrects the error of the error locations corresponding to the obtained roots.