Memory Controller Multiple Read Error Correction
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Solution Overview
Problem
Solid state drives (SSDs) using NAND type flash memory face challenges in reducing the bit error rate, which affects their performance and lifespan, due to the overlap of threshold voltage peaks leading to incorrect read values during single read operations.
Innovation Solution
A memory system with a memory controller that performs multiple read processes with varying error correction capabilities, including single, coarse, and fine Vth tracking, to statistically determine the correct bit information by accumulating read values and using error correction codes to correct errors, thereby reducing the bit error rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single read operation is performed, then the read speed is fast, but the bit error rate increases due to threshold voltage peak overlap
Solution Approach 1:
The patent implements multiple periodic read operations instead of a single read. The memory controller performs a first read operation, then a second read operation, and optionally a third read operation at different time points. By periodically reading the same data multiple times and comparing the results, the system can identify and correct bit errors caused by threshold voltage fluctuations, thereby reducing the bit error rate while maintaining acceptable read speed through parallel processing and optimization.
2Reliability
If multiple read processes are performed to reduce bit error rate, then the reliability improves, but the read time increases
Solution Approach 1:
The patent segments the error correction process into distinct stages. The first read operation uses a first error correction code (ECC) with a certain correction capability. If errors are detected, a second read operation is performed with a second ECC that has different correction characteristics. This segmentation allows the system to handle different error scenarios efficiently, reducing the average read time compared to always performing multiple reads with uniform error correction.
Solution Approach 2:
The patent applies partial action by conditionally performing read operations. Instead of always performing three reads, the system performs a first read, and only performs additional reads if error correction is needed. The counter tracks the number of reads performed, and the process can be terminated early if successful correction is achieved, thus reducing the average time loss while still improving reliability when necessary.
3Reliability
If error correction codes are used to correct read errors, then the bit error rate decreases, but the processing complexity increases
Solution Approach 1:
The patent changes the error correction parameters dynamically based on the read situation. Different error correction codes with varying strengths and processing complexities are selected for different read operations. The memory controller adjusts the ECC parameters (such as code rate, block size, and correction capability) according to the detected error patterns and the number of reads performed, optimizing the balance between reliability improvement and processing complexity.
Data Source
AI summary
According to one embodiment, a memory controller of a memory system includes a command issuing unit, a decoder, a counter, and a statistical processor. The command issuing unit issues a first command for single read of first data from a nonvolatile memory. The decoder performs first error correction on the read first data. The counter counts a number of times of multiple reads. The statistical processor performs statistical processing of results of the multiple reads, and outputs second data obtained by the statistical processing. When the decoder is unable to perform the first error correction on the read first data, the command issuing unit issues a second command for multiple reads of the first data.