Memory Controller Scheduling for Multithread Applications

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Solution Overview

Problem

Current memory scheduling schemes fail to optimize memory access for multithread applications, leading to performance degradation due to their inability to recognize and prioritize threads within multithread applications, which results in inefficient use of multi-core processors.

Innovation Solution

A memory controller that identifies multithread applications and adjusts the memory scheduling scheme by determining the number of idle threads in different thread groups, ranking them based on idle threads, and prioritizing memory requests from higher-ranked groups over lower-ranked groups to ensure efficient resource allocation and utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional memory scheduling schemes (FRFCFS or PAR-BS) are used, then memory controller performance is optimized for single-thread applications, but performance degrades for multithread applications due to inability to recognize and prioritize threads

Engineering Contradiction:
Improvememory controller performanceVSAvoidapplicability to multithread applications
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The memory scheduling scheme dynamically adapts its behavior based on the detected thread type. The controller transitions between different scheduling modes (FRFCFS for single-thread, application-aware scheduling for multithread) depending on runtime conditions, allowing optimal performance across different application types without sacrificing either single-thread or multithread optimization capability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the scheduling parameters and priority rules based on the application type detected. For multithread applications, the controller modifies memory request prioritization logic to consider thread group membership and idle thread status, transforming the static scheduling parameters into adaptive ones that respond to application characteristics

Inventive Principle:
Principle #35Parameter changes

2Reliability

If memory requests are prioritized based on traditional scheduling rules, then single-thread application performance is maintained, but multithread application throughput decreases due to inefficient resource allocation

Engineering Contradiction:
Improvesingle-thread performance consistencyVSAvoidmultithread application throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory controller implements feedback mechanisms by monitoring thread execution status and idle thread conditions. This feedback information is used to dynamically adjust memory request prioritization, ensuring that multithread applications receiving memory service when they have idle threads ready, thereby improving throughput while maintaining fairness for single-thread applications

Inventive Principle:
Principle #23Feedback

3Device complexity

If memory scheduling does not consider thread idle status, then scheduling simplicity is maintained, but core idle time increases and system throughput decreases

Engineering Contradiction:
Improvescheduling scheme complexityVSAvoidcore idle time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The memory controller performs preliminary detection and classification of application types before executing memory requests. By identifying multithread applications and their idle thread status in advance, the controller can proactively adjust scheduling priorities to prevent core idle time, rather than reacting after delays occur

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention introduces an intermediary scheduling layer between the memory requests and the memory controller that analyzes thread group composition and idle status. This intermediary component bridges the simple FRFCFS mechanism and the complex multithread optimization needs, adding intelligence without completely redesigning the underlying scheduling infrastructure

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2580669B1Multithread application-aware memory scheduling scheme for multi-core processors
Publication Date: 2018.07.25 ADVANCED MICRO DEVICES INC
  • EP2580669B1 patent drawingFigure 1
  • EP2580669B1 patent drawingFigure 2
  • EP2580669B1 patent drawingFigure 3

AI summary

A device may include a memory controller that identifies a multithread application, and adjusts a memory scheduling scheme for the multithread application based on the identification of the multithread application.