Memory Controller Command Scheduling for DRAM Transfer Efficiency
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Solution Overview
Problem
Conventional methods for writing data in DRAM using LPDDR4 suffer from inefficiencies, particularly when dealing with data sizes smaller than a predetermined size, leading to increased overhead and reduced memory access efficiency due to the generation of Masked Write (MWR) commands, which can result in unintended overwriting and increased transfer data amounts.
Innovation Solution
A memory controller that issues separate write commands for data of predetermined and smaller sizes, determining whether a subsequent write command can be issued within the penalty period of an MWR command, and if so, issuing it before the MWR command to optimize data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dummy data is provided to make transfer size equal to predetermined size, then the penalty of small data transfer is reduced, but unintended overwriting occurs and transfer data amount increases
Solution Approach 1:
The patent applies preliminary action by checking whether a subsequent write command can be issued within the penalty period before actually issuing the MWR command. The controller determines in advance if the timing conditions are met, and only then issues the MWR command, thereby avoiding the need for dummy data while preventing unintended overwriting.
Solution Approach 2:
The patent changes the parameter of command issuance timing by issuing the MWR command before the subsequent write command when timing conditions are met, rather than following the conventional sequence. This parameter change in command timing eliminates the penalty without requiring dummy data expansion.
2Ease of operation
If MWR command is used for small data transfer, then data writing is achieved, but memory access efficiency is reduced due to long penalty period
Solution Approach 1:
The patent maintains continuity of useful action by overlapping the MWR command execution with subsequent write operations. By issuing the subsequent write command during the penalty period of the MWR command when timing conditions are met, the system ensures continuous data transfer without idle waiting periods, thereby maintaining high memory access efficiency.
Solution Approach 2:
The patent introduces dynamics by making the command issuance strategy adaptive based on timing conditions. The controller dynamically determines whether to issue the MWR command before or after the subsequent write command based on whether the subsequent command can be issued within the penalty period, optimizing memory access efficiency for different scenarios.
3Ease of manufacture
If MWR command is issued to the same bank after preceding WR/MWR command, then data writing is performed, but 4 times longer interval is required compared to conventional WR command
Solution Approach 1:
The patent applies preliminary action by checking the timing feasibility before issuing the MWR command. The controller determines in advance whether the subsequent write command can be issued within the penalty period, and only issues the MWR command if this condition is met, thereby reducing the effective command interval from 4x to 1x the conventional WR command interval.
Data Source
AI summary
A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.