Memory Controller Parallel NAND Flash Interleaving
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Solution Overview
Problem
NAND flash memory access speeds are slow compared to DRAMs and CPUs, and interleaving access to multiple NAND flash arrays is challenging due to inflexible sector size constraints in some systems.
Innovation Solution
A memory controller method that reorganizes write and read commands to enable concurrent, parallel access to multiple non-volatile memory arrays by identifying data groups for simultaneous writing across arrays, excluding data that cannot be interleaved, and executing commands in a way that allows for efficient interleaving even in systems with hardware or software constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is used to increase storage capacity, then storage density is improved, but write speed becomes slow compared to DRAM and CPU operating speeds
Solution Approach 1:
The patent divides a single large write operation into multiple smaller write operations that can be distributed across multiple NAND flash chips. The data is segmented into chunks that can be written in parallel to different chips, effectively increasing the overall write speed while maintaining high storage capacity.
Solution Approach 2:
The patent combines multiple NAND flash chips into a unified storage system managed by a single controller. By merging the capabilities of multiple chips and coordinating their operations through interleaving, the system achieves both high storage capacity and improved write speed through parallel operations.
2Speed
If interleaving access is implemented to improve access times, then speed is improved, but system complexity increases due to inflexible sector size constraints
Solution Approach 1:
The patent implements dynamic interleaving where the controller can adjust the interleaving parameters and data distribution strategy based on the specific operation requirements and system state. This dynamic approach allows the system to optimize for speed while adapting to different sector size constraints, reducing the perceived complexity through intelligent resource management.
Solution Approach 2:
The patent changes the parameters of the write operations, specifically the data chunk sizes and distribution patterns, to be compatible with the existing sector size constraints of the NAND flash chips. By adjusting these parameters, the system can implement interleaving access to improve speed without requiring changes to the underlying hardware constraints.
3Productivity
If parallel concurrent access to multiple NAND flash arrays is implemented, then productivity is improved, but difficulty of operation increases due to inflexible sector size requirements
Solution Approach 1:
The patent introduces a sophisticated controller as an intermediary between the host system and the NAND flash arrays. This mediator handles the complexity of parallel access coordination, data distribution, and sector size matching, allowing the host system to operate with simple, flexible interfaces while the intermediary manages the parallel operations to improve productivity.
Solution Approach 2:
The patent creates a universal interface layer that can handle different sector size requirements and interleaving configurations through a single unified controller. This multi-functional approach allows the system to maintain ease of operation with a standard interface while supporting various parallel access configurations to improve productivity.
Data Source
AI summary
A memory controller (16) is used in a system (10) having a main memory (22) and a set of non-volatile memories (26, 32, 38, 44). Each non-volatile memory comprises a plurality of sectors (S0-S28), pages, or other memory unit types. A command is received to write data to the set of non-volatile memories (26, 32, 38, 44). Within the data is identified a grouping of the data that is for writing to sectors in the set of non-volatile memories in which each non-volatile memory of the set of non-volatile memories is to be written and each sector to be written has a corresponding location to be written in all of the other non-volatile memories. Corresponding locations are locations that are in the same location in the sequential order. The grouping of data is written into the set of the non-volatile memories to result in the writing in the non-volatile memories occurring contemporaneously.