Memory Controller NoC Topology for High-Bandwidth Routing
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Solution Overview
Problem
As programmable logic devices increase in size and complexity, the interconnect resources become insufficient to handle the increased amount of data exchanged between cores and external devices, leading to bottlenecks and inefficiencies in memory access.
Innovation Solution
Implementing a Network-on-Chip (NoC) topology with dedicated memory interfaces and virtual channels to facilitate flexible routing and prioritize data packets, allowing direct communication between cores and memory controllers, and employing bridges and bypass modes for efficient data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated interconnects are used to connect data processing circuits to memory, then reliability of memory access is improved, but device complexity increases and routing resources become insufficient
Solution Approach 1:
The interconnect network is segmented into multiple routing resources (horizontal and vertical interconnects) that can independently handle different data traffic streams. This segmentation allows the system to maintain reliable memory access through distributed routing paths while managing complexity by dividing the overall routing function into manageable segments.
Solution Approach 2:
The routing resources are designed to be universal and multi-functional, serving both memory access operations and inter-core communication. By making the same routing infrastructure serve multiple purposes, the system achieves reliable memory access without proportionally increasing routing resource complexity.
2Productivity
If the number of functional blocks and processing speed are increased, then productivity is improved, but routing resources become insufficient and bottlenecks occur
Solution Approach 1:
The routing architecture transitions from a planar two-dimensional interconnect to a three-dimensional routing structure by adding vertical interconnects that pass through multiple layers. This dimensional expansion provides additional routing paths that scale with processing speed requirements without proportionally increasing routing resource complexity.
Solution Approach 2:
The routing resources are designed to be dynamically configurable, allowing the system to adapt routing paths based on real-time traffic demands. This dynamic allocation enables the routing infrastructure to handle increased productivity requirements by efficiently utilizing existing resources rather than requiring proportional increases in routing capacity.
3Quantity of substance
If more routing resources are added to handle increased data exchange, then data exchange capacity is improved, but device complexity and bottleneck formation increase
Solution Approach 1:
Multiple routing functions are merged into a unified routing fabric that handles both memory access and core-to-core communication. By combining these functions into a single integrated routing system rather than separate dedicated paths, the architecture increases data exchange capacity while reducing the complexity of managing multiple independent routing subsystems.
Data Source
AI summary
Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.