Memory Controller Redundant NVRAM Mapping for Latency Reduction
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Solution Overview
Problem
Current NVRAM interface technologies, such as PCI Express, introduce latency and performance limitations due to packet-based transactions, which are critical in gaming applications where read cycles are often the bottleneck, and existing solutions do not adequately address data integrity and corruption issues in environments requiring high data integrity like slot machines.
Innovation Solution
A memory controller that redundantly maps multiple NVRAM banks to a memory space, allowing independent execution of memory operators for functions like hash checks, data integrity checks, and block copies, using field programmable gate arrays (FPGAs) to reduce latency and enhance data integrity, with dual modes of operation for direct and managed memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCI Express interface technology is used for NVRAM, then data transfer speed is improved, but latency increases and performance is limited due to packet-based transactions
Solution Approach 1:
The patent segments the memory system into multiple independent NVRAM banks (Bank 0, Bank 1, Bank 2) that can be accessed simultaneously. This parallel architecture allows the system to overcome the latency limitations of packet-based PCI Express transactions by distributing memory operations across multiple banks, thereby reducing overall access time while maintaining high data transfer speeds.
Solution Approach 2:
The patent implements preliminary action by pre-fetching data from NVRAM banks into CPU cache memory before the CPU actually needs it. The memory controller monitors CPU access patterns and proactively loads data into the cache, so that when the CPU requests the data, it is already available in fast cache memory rather than waiting for slow NVRAM access or packet-based PCI Express transactions.
2Reliability
If multiple identical copies of data are maintained in NVRAM banks, then data integrity is improved, but data transfer volume and processing overhead increase
Solution Approach 1:
The patent extracts the integrity verification function from the main CPU processing flow and implements it as a dedicated memory operator within the memory controller. This specialized operator can verify data integrity across multiple NVRAM banks independently of the CPU, eliminating the need for the CPU to manually compare data copies and reducing processing overhead while maintaining comprehensive data integrity checking.
Solution Approach 2:
The memory controller implements self-service by autonomously managing data integrity verification across NVRAM banks without requiring CPU intervention. The memory operator automatically detects and corrects errors in stored data, and the controller handles all redundancy management tasks independently, freeing the CPU from these overhead operations while ensuring data integrity is maintained.
3Reliability
If NVRAM operations are performed to maintain data integrity, then reliability is improved, but system responsiveness deteriorates due to CPU blocking
Solution Approach 1:
The patent introduces an intermediary layer in the form of CPU cache memory and a sophisticated memory controller that mediates between the CPU and NVRAM banks. The cache memory acts as a buffer that decouples CPU operations from slow NVRAM access, allowing the CPU to continue executing instructions without being blocked by NVRAM operations. The memory controller manages data integrity verification in the background, ensuring reliability while maintaining system responsiveness.
Solution Approach 2:
The patent replaces the traditional mechanical blocking mechanism (where CPU must wait for NVRAM operations to complete) with a parallel processing architecture. Multiple memory operators execute data integrity verification and memory management tasks simultaneously with CPU operations, substituting the sequential blocking model with a concurrent parallel model that maintains both reliability and responsiveness.
4Speed
If conventional RAM is used for fast access, then speed is improved, but data loss occurs during power failure events
Solution Approach 1:
The patent merges the speed characteristics of conventional RAM with the data persistence of NVRAM by creating a hybrid memory system. NVRAM banks provide non-volatile storage that retains data during power failures, while the CPU cache memory provides fast access for active data. The memory controller intelligently manages this merged system, allowing the CPU to access frequently used data from fast cache while critical data resides in persistent NVRAM, achieving both speed and reliability simultaneously.
Data Source
AI summary
A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).