Memory Controller Omitting Status Checks to Reduce Read Latency
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Solution Overview
Problem
The existing memory systems face delays in read operations due to the time required for status polling operations, which hinder efficient data retrieval from non-volatile memory chips.
Innovation Solution
The memory controller initiates data transfer operations without checking the status of memory chips once the set operation period for sense operations expires, utilizing timers to manage sense operation periods based on write modes or page types, allowing for timely data transfer without waiting for status updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller performs status polling operations to check the status of memory chips, then the reliability of data transfer is ensured, but the read operation time increases due to waiting for status updates
Solution Approach 1:
The memory controller pre-sets timer values corresponding to different write modes and page types before initiating sense operations. When a sense operation is started, the appropriate timer value is already available, allowing the controller to immediately start the timer without waiting for status checks, thus resolving the contradiction between reliability and time loss
Solution Approach 2:
The timer automatically tracks the sense operation duration and generates completion signals without requiring continuous status polling by the memory controller. This self-service mechanism ensures reliable data transfer timing while eliminating the time-consuming status check loop
2Measurement precision
If the memory controller waits for status updates before initiating data transfer, then the accuracy of transfer timing is maintained, but the read operation efficiency decreases
Solution Approach 1:
The system pre-calculates and stores timer values for different sense operation conditions (write modes and page types) before actual operations occur. This preliminary preparation allows the memory controller to achieve both precise timing and high efficiency by simply comparing the current operation type against pre-stored timer values without waiting for status updates
Solution Approach 2:
The timer mechanism dynamically adapts to different sense operation durations by selecting appropriate pre-stored timer values based on write modes and page types. This dynamic selection maintains timing accuracy for varying operation lengths while enabling parallel processing and improving overall read operation efficiency
3Adaptability or versatility
If the memory controller stores timer values for different write modes and page types, then the adaptability to various operation conditions is improved, but the memory resource consumption increases
Solution Approach 1:
A single timer resource is designed to serve multiple different sense operation conditions by pre-storing timer values for various write modes and page types. This universal timer can be configured for different operations without requiring separate dedicated timers for each condition, thus achieving high adaptability with minimal memory resource consumption
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of parallel operation elements each including a memory cell. The memory controller is configured to control the plurality of parallel operation elements. In reading data from the non-volatile memory, the memory controller is configured to sequentially instruct the plurality of parallel operation elements to perform a sense operation of sensing data stored in the memory cell included in each of the plurality of parallel operation elements. In a case where an operation period of the sense operation of any one of the plurality of parallel operation elements is expired, the memory controller instructs the one of the plurality of parallel operation elements to perform a transfer operation for the data without checking a status of the one of the plurality of parallel operation elements.