Memory Controller Platform Error Correction via On-Die ECC Segmentation
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Solution Overview
Problem
The increasing density of memory technology leads to more frequent data refreshing needs, causing performance issues due to increased computational resource usage and potential interference with on-die error correction codes, which can affect system memory controllers.
Innovation Solution
A system with a memory controller that interacts with on-die ECC to optimize memory scrubbing operations by adjusting stride lengths and error correction capabilities, allowing for efficient multi-level ECC and reduced processor cycles, address bus bandwidth, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to improve storage capacity, then storage density is improved, but data reliability deteriorates due to increased need for frequent refreshing and scrubbing
Solution Approach 1:
The patent implements multi-level ECC by dividing error correction into two segments: on-die ECC for immediate error correction at the memory chip level, and platform ECC for additional protection at the memory controller level. This segmentation allows the system to maintain high storage density while improving data reliability through layered error correction mechanisms.
Solution Approach 2:
The patent performs preliminary error correction at the on-die level before data reaches the platform memory controller. By correcting errors early in the data path, the system prevents error propagation and reduces the burden on platform ECC, thereby maintaining reliability at high density without excessive scrubbing overhead.
2Reliability
If frequent memory scrubbing is performed to improve data reliability, then data reliability is improved, but system performance deteriorates due to increased computational resource usage
Solution Approach 1:
The patent enables the memory device to perform self-service error correction through on-die ECC capabilities. The memory chip autonomously detects and corrects errors before data leaves the die, eliminating the need for frequent platform-level scrubbing operations and maintaining system performance while ensuring data reliability.
Solution Approach 2:
The on-die ECC acts as an intermediary between the memory array and the platform memory controller. It handles error correction locally, preventing errors from reaching the platform level and reducing the computational burden on the system memory controller, thereby maintaining both reliability and performance.
3Reliability
If on-die ECC is enabled to improve error correction capability, then data reliability is improved, but interference with platform memory controller operations occurs
Solution Approach 1:
The patent implements a feedback mechanism where the memory device signals error status to the platform memory controller after on-die ECC processing. This feedback allows the controller to understand which errors were corrected locally and which require platform-level attention, simplifying controller operations while maintaining enhanced error correction capability.
Solution Approach 2:
The patent extracts error correction functionality from the platform memory controller and places it at the on-die level. This extraction reduces the operational complexity of the platform controller by removing the burden of comprehensive error management, while the on-die ECC handles routine error correction independently.
Data Source
AI summary
An example device includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.