Memory Controller Operation Mode Switching for Predictable Host Delays

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Solution Overview

Problem

Memory systems face challenges in predicting and managing background operations, leading to increased delay times that hosts cannot anticipate, affecting the quality of service (QoS) due to unpredictable execution of garbage collection, read-reclaim, and wear leveling operations by memory controllers.

Innovation Solution

A memory system and controller that calculate read-attribute, write-attribute, and time-attribute values to determine operation modes, allowing the controller to decide whether to execute background operations, thereby enabling hosts to predict and prepare for potential delays and maintain high QoS by switching between operation modes based on threshold values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory controller executes background operations (garbage collection, read-reclaim, wear leveling), then memory system reliability and performance are improved, but the delay time for processing host commands increases and becomes unpredictable

Engineering Contradiction:
Improvememory system reliabilityVSAvoiddelay time for processing host commands
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory controller dynamically adjusts its operation mode based on real-time monitoring of memory block states and host command patterns. When background operations are needed, the controller switches to a mode that executes them; when host commands require priority, it switches to a mode that minimizes background operations, thereby adaptively managing the trade-off between reliability maintenance and response time

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory controller performs background operations in advance during periods of low host activity or when memory blocks are identified as needing maintenance before they cause failures. By proactively executing garbage collection, read-reclaim, and wear leveling operations before critical thresholds are reached, the system maintains reliability while reducing the likelihood of delays during high-demand periods

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the memory controller performs background operations continuously, then memory block health and performance are maintained, but the host cannot predict processing delays affecting quality of service

Engineering Contradiction:
Improvememory block healthVSAvoidpredictability of processing delays
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The memory controller implements a feedback mechanism that continuously monitors the state of memory blocks (including read counts, write counts, and error rates) and adjusts background operation execution accordingly. This feedback loop allows the controller to maintain memory health by executing background operations only when monitoring data indicates they are needed, while providing predictable behavior by avoiding unnecessary operations that would cause unpredictable delays

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes operational parameters such as the frequency and intensity of background operations based on monitored memory block parameters. When memory blocks show signs of degradation (high read/write counts, error patterns), the controller increases background operation frequency; when blocks are healthy, it reduces frequency, thereby maintaining reliability while improving predictability of host command processing times

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11500562B2Memory system, memory controller, and operation method thereof utilizing at least first and second operational modes
Publication Date: 2022.11.15 SK HYNIX INC
  • US11500562B2 patent drawing
  • US11500562B2 patent drawing
  • US11500562B2 patent drawing

AI summary

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.