Memory Controller Mode Switching for OS Data Storage

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Solution Overview

Problem

Current memory systems lack the ability to easily enable or disable a pre-coding mode based on host interface mode changes, which affects the efficient storage and retrieval of OS code data and normal data, leading to suboptimal performance in varying data transmission speeds.

Innovation Solution

A memory system with a controller that selects between pre-coding and normal write modes in response to host interface mode commands, allowing OS code data to be stored in an OS region during pre-coding mode and normal data in a separate region, with the controller managing data storage and retrieval based on the host interface mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If pre-coding mode is enabled for storing OS code data, then data transmission speed is improved, but device complexity increases due to mode switching requirements

Engineering Contradiction:
Improvedata transmission speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory system dynamically switches between pre-coding mode and normal write mode based on the type of data being written. The controller identifies whether incoming data is OS code data or normal data and automatically selects the appropriate writing mode, enabling adaptive optimization without manual configuration or complex fixed architecture

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (writing mode) based on data type. When OS code data is detected, the controller activates pre-coding mode with specific voltage levels and timing parameters optimized for code data integrity. For normal data, standard write parameters are used, allowing parameter optimization without permanent structural complexity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If separate OS region is used for storing OS code data, then data reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The memory device is segmented into an OS region and a normal region, allowing OS code data to be stored in the dedicated OS region with enhanced reliability features. This logical segmentation enables different storage characteristics for different data types without requiring physically separate manufacturing processes, as both regions use the same memory cell structure but are managed differently by the controller

Inventive Principle:
Principle #1Segmentation

3Speed

If pre-coding mode is used for OS code data storage, then data transmission speed is improved, but ease of operation worsens due to mode management complexity

Engineering Contradiction:
Improvedata transmission speedVSAvoidease of operation
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The controller automatically determines whether incoming data is OS code data or normal data and self-manages the mode switching between pre-coding mode and normal write mode. This self-service capability eliminates the need for external mode configuration or complex user management, maintaining ease of operation while enabling speed optimization through automatic adaptive mode selection

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10705746B2Memory system and operating method thereof
Publication Date: 2020.07.07 SK HYNIX INC
  • US10705746B2 patent drawing
  • US10705746B2 patent drawing
  • US10705746B2 patent drawing

AI summary

A memory system includes: a controller for selecting a pre-coding mode or a normal write mode in response to a host interface mode change command inputted from a host device; and a semiconductor memory device for storing, in an operating system (OS) storage area, OS data inputted from the host device in the pre-coding mode under the control of the controller.