Memory Controller Oversampling Calibration Timing Shift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern memory systems face timing shifts due to implementation differences, temperature, and voltage effects, particularly in DDR memory, where there is no standard method for calibrating data transfer between memory and memory controllers.
Innovation Solution
A memory controller with an oversampling circuit that samples data at a higher frequency to determine timing shifts, using a calibration data pattern to adjust the sampling window and control data transfer, eliminating the need for analog delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer frequency is increased to improve memory performance, then productivity is improved, but timing shifts and synchronization issues worsen
Solution Approach 1:
The patent applies preliminary action by performing timing calibration before actual data transfer operations. The memory controller calibrates the sampling window position in advance by comparing read data with expected data patterns, determining the optimal sampling point before high-speed transfers begin. This pre-calibration ensures that subsequent high-frequency transfers maintain proper synchronization without timing errors.
Solution Approach 2:
The patent implements feedback by using the comparison result between read data and expected data patterns to adjust the sampling window position. The memory controller reads calibration data, compares it with expected patterns, determines the timing shift, and then adjusts the sampling window accordingly. This closed-loop feedback mechanism ensures that timing synchronization is maintained even at increased data transfer frequencies.
2Manufacturing precision
If analog delay lines are used to adjust timing, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/analog delay line system with a digital/software-based solution. Instead of using physical analog circuits to adjust timing, the memory controller uses a calibration routine that reads data, compares it with expected patterns, calculates the timing shift, and adjusts the sampling window position through digital control. This substitution eliminates complex analog timing adjustment circuits while achieving precise timing control through software/firmware logic.
3Ease of manufacture
If calibration method is standardized to improve ease of manufacture, then ease of manufacture is improved, but adaptability to different memory types decreases
Solution Approach 1:
The patent achieves universality by designing a calibration method that works across different memory types and vendors. The approach uses a generic calibration routine that reads calibration data, compares it with expected patterns, and adjusts timing based on the determined shift. This universal method can be applied to various memory interfaces (SDHC, SDXC, UHS-I, UHS-II) and memory types without requiring vendor-specific or type-specific calibration procedures, thus maintaining both ease of manufacture and adaptability.
Data Source
AI summary
A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.