Memory Controller for Packet Applications with Consecutive Burst Storage
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Solution Overview
Problem
Current memory controllers for packet buffering in communications networks face inefficiencies due to high latency and complexity in managing DRAM banks, particularly with linked list approaches that are prone to errors and bank access conflicts, leading to suboptimal memory throughput.
Innovation Solution
A memory controller architecture that stores full packets as data bursts in consecutive memory locations, allowing for out-of-sequence access and automatic overwriting, reducing the need for complex pointer management and minimizing bank access conflicts, thereby achieving higher memory efficiency and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If linked list management is used to store packet fragments in random memory locations, then memory flexibility is improved, but device complexity increases and reliability decreases due to pointer corruption risks
Solution Approach 1:
The patent segments memory into dedicated buffers for different packet states (arrived, reading, writing, retransmitting) rather than using a unified linked list structure. Each buffer has fixed-size entries with predetermined fields, eliminating the need for dynamic pointer management while maintaining the ability to organize and access packet data efficiently.
Solution Approach 2:
The patent uses fixed-size buffer entries that can be easily overwritten and reused. When a buffer entry is no longer needed (packet transmitted or discarded), it is simply overwritten by new packet data without requiring complex memory management or pointer updates, making the system more robust and simpler to implement.
2Adaptability or versatility
If linked list management is used to store packet fragments, then memory adaptability is improved, but reliability worsens due to corruption risks
Solution Approach 1:
By segmenting memory into dedicated buffers with fixed structures, the patent eliminates pointer-based links that are susceptible to corruption. Each buffer entry is self-contained with explicit state indicators, making the system more reliable while still adaptable to different packet handling requirements through state transitions.
Solution Approach 2:
The patent incorporates state flags and validation fields in each buffer entry that anticipate and prevent corruption issues before they occur. The fixed structure includes built-in checks for data validity and state consistency, providing a cushion against reliability failures without requiring complex error handling mechanisms.
3Productivity
If packet fragments are stored in random memory locations, then bank access conflicts are reduced, but device complexity increases due to management overhead
Solution Approach 1:
The patent segments buffers into fixed-size entries with explicit state fields that indicate which memory bank and location should be accessed next. This segmentation allows the controller to systematically manage access to multiple banks without complex algorithms, maintaining high throughput through structured, predictable access patterns.
Solution Approach 2:
The patent uses dynamic state flags in each buffer entry that automatically adjust memory access patterns based on current packet processing needs. The state machine approach allows the system to adaptively switch between different memory banks and access modes without requiring complex external management logic, balancing throughput and simplicity.
4Productivity
If multiple packets share common linked lists, then memory efficiency is improved, but device complexity increases due to maintenance requirements
Solution Approach 1:
The patent segments the shared memory space into independently manageable buffer entries, each with its own state indicators. Multiple packets can share the same physical memory region through different buffer entries, but each entry is self-contained with explicit state fields, eliminating the need for complex linked list maintenance while preserving memory efficiency through sharing.
Data Source
AI summary
A method and apparatus for accessing and storing data in a memory are disclosed. The system includes a memory controller coupled to a memory having locations characterized by banks and lines. The memory controller is configured for storing a data packet with data bursts in sequence in consecutive memory locations, while providing the capability of reading or writing data bursts out of sequence by accessing the consecutive memory locations in a random order.