Memory Controller Data Transfer via Acknowledgement
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Solution Overview
Problem
In existing data transfer systems using DMA Controllers, peripheral modules often become congested due to data packets being blocked when there is no available memory space for certain classifications, even if there is space for other classifications, leading to inefficient operation.
Innovation Solution
The method involves the memory-controller sending an acknowledgement to the peripheral module to transmit data packets regardless of available memory space, with the option to store or discard the packets based on space availability, preventing congestion and ensuring smooth operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data packets are transferred sequentially from peripheral modules to memory via DMA Controller, then data transfer follows FIFO order, but peripheral modules become congested when earlier packets block later packets due to classification-specific memory space unavailability
Solution Approach 1:
The system performs preliminary classification of data packets into different queues based on their destination memory space requirements. By pre-organizing packets into classification-specific queues before transfer, the system enables selective transmission of packets that can be accommodated in available memory space, preventing congestion caused by blocking packets regardless of their memory availability status.
Solution Approach 2:
The invention segments the single data transfer queue into multiple classification-specific queues within the peripheral module. Each queue corresponds to a specific memory space classification. This segmentation allows the DMA controller to selectively transfer packets from appropriate queues based on current memory availability, preventing high-priority packets from blocking low-priority packets that could be immediately transferred.
2Productivity
If the DMA Controller checks memory space availability before each data packet transfer, then memory space is efficiently utilized, but transfer speed decreases due to repeated checking
Solution Approach 1:
The system performs preliminary determination of memory space availability for each classification at the start of the transfer process. The DMA controller checks which memory spaces are available and loads corresponding packet queues into buffers in advance. This preliminary action eliminates the need for repeated space availability checks during packet transmission, significantly improving transfer speed while maintaining efficient memory utilization.
Solution Approach 2:
The system dynamically adjusts the transfer process by monitoring memory space availability and adaptively selecting which packet queues to transfer. The DMA controller can switch between different classification queues based on real-time memory status, optimizing both transfer speed and memory utilization without requiring continuous checking of each packet's destination space.
3Ease of manufacture
If memory space is allocated for specific packet classifications, then memory management is organized and efficient, but packets of other classifications are blocked even when memory space exists for their classification
Solution Approach 1:
The invention segments both memory space and packet queues by classification. Multiple classification-specific queues are maintained in the peripheral module, each corresponding to a specific memory space type. This dual segmentation ensures that packets from different classifications are independently managed and transferred, preventing cross-classification blocking while maintaining organized memory allocation for each packet type.
Solution Approach 2:
The system applies local quality management by treating each packet classification with specialized handling tailored to its specific memory requirements. Each classification queue is managed independently with its own transfer logic, allowing optimal treatment for each packet type based on its destination memory characteristics, thereby improving overall system smoothness while maintaining organized memory management.
Data Source
AI summary
There is provided an apparatus and method for transferring data packets from a peripheral module to a memory via a memory-controller. When a given peripheral module requests that it send a data packet to the memory via the memory-controller, the memory-controller sends an acknowledgement indicating that the peripheral module can send the data packet, whether or not there is a descriptor for the data packet. If there is a descriptor, the memory-controller receives the data packet from the peripheral module and stores it in the memory. If there is not a descriptor, the memory-controller discards the data packet as it receives it. Thus, whether or not there is a descriptor available for the data packet, the peripheral module still sends the data packet to the memory-controller. The data packets may be assigned classifications and each classification may be assigned a dedicated space in the memory.