Memory Controller Dynamic Page Size Selection
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Solution Overview
Problem
Current memory devices, such as DRAM, have fixed page sizes, leading to inefficient data access due to the inability to adapt to varying data characteristics, resulting in unnecessary time delays and reduced performance.
Innovation Solution
A memory system with multiple memory dies and banks of different page sizes, controlled by a memory controller that generates chip selection or page control signals based on the reordering number of requests from a processor, allowing dynamic selection of the appropriate page size for optimal data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed page size is used in DRAM, then the memory access time is predictable and simple, but the data access efficiency deteriorates due to inability to adapt to varying data characteristics
Solution Approach 1:
The memory device is divided into multiple memory banks (first memory bank, second memory bank, third memory bank) with different page sizes. This segmentation allows the system to select the appropriate bank based on data characteristics, improving access efficiency without requiring a single complex adaptive structure.
Solution Approach 2:
Each memory bank is configured with a specific page size characteristic (first bank with larger page size, second bank with medium page size, third bank with smaller page size). This local quality differentiation enables optimal matching between data access patterns and memory structure, resolving the contradiction between efficiency and complexity.
2Productivity
If a larger page size is used, then fewer memory access operations are needed for large data, but the memory access time increases due to activating more bit lines
Solution Approach 1:
Different memory banks are assigned different page sizes based on access patterns. The first memory bank with larger page size handles data requiring high throughput, while the third memory bank with smaller page size handles data requiring fast activation. This local optimization resolves the time-throughput tradeoff.
Solution Approach 2:
The memory controller dynamically selects which memory bank to activate based on the characteristics of the data being accessed. This dynamic adaptation allows the system to optimize between page activation time and access throughput in real-time, preventing the fixed tradeoff.
3Productivity
If multiple memory banks with different page sizes are provided, then data access efficiency is improved through selective activation, but the device complexity increases
Solution Approach 1:
The memory device is segmented into three distinct memory banks, each with a different page size configuration. This segmentation provides the flexibility to match various data access patterns while maintaining a manageable level of complexity through systematic organization.
Solution Approach 2:
The multiple memory banks with different page sizes provide universal functionality to handle various data access patterns (sequential access, random access, large data blocks, small data blocks). This multi-functionality improves overall access efficiency without requiring separate specialized memory devices for each access pattern.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies having different page sizes. The memory controller generates a plurality of chip selection signals for activating the plurality of memory dies based on the reordering number of requests received from a processor.