Memory Controller Page Write Optimization
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Solution Overview
Problem
Existing memory controllers face inefficiencies in read performance due to data being divided and stored across multiple memory chips, leading to slower read operations and increased drive times when commands are queued randomly across submission queues.
Innovation Solution
A memory controller architecture that identifies the remaining space in a memory page and fetches write commands from dedicated submission queues based on this space, ensuring data is stored in a single memory chip, thereby preventing data division across chips and optimizing read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored across multiple memory chips to increase storage capacity, then storage capacity is improved, but read performance deteriorates due to data division across chips
Solution Approach 1:
The patent divides the storage system into multiple memory chips while implementing a command queue management mechanism that segments write commands into dedicated queues. Each queue is associated with specific memory chips, ensuring that data from a single command is written to chips in a controlled sequence, preventing random data division that degrades read performance.
Solution Approach 2:
The patent establishes dedicated submission queues before write operations begin, pre-organizing write commands based on their target memory chips. This preliminary organization ensures that when data is written, it follows a predictable pattern that maintains read performance while achieving high storage capacity through multi-chip architecture.
2Reliability
If write commands are processed sequentially to ensure data integrity, then reliability is improved, but productivity deteriorates due to slower write operations
Solution Approach 1:
The patent segments the submission queue into multiple dedicated queues, each handling specific write commands for particular memory chips. This segmentation allows parallel processing of write commands across different queues while maintaining data integrity within each queue, thus improving write speed without sacrificing reliability.
Solution Approach 2:
The patent implements a dynamic queue management system where the controller can selectively access different submission queues based on the current write operation requirements. This dynamic approach enables the system to switch between sequential processing for integrity-critical operations and parallel processing for performance-critical operations, balancing reliability and productivity.
3Productivity
If multiple submission queues are used to increase throughput, then productivity is improved, but device complexity increases due to queue management overhead
Solution Approach 1:
The patent designs the submission queue structure with universal characteristics where each dedicated queue follows the same management protocol and data format. This universality allows the memory controller to handle multiple queues using a single, standardized management mechanism, increasing throughput while minimizing the complexity overhead associated with managing multiple different queue types.
4Loss of substance
If data is divided across memory chips to utilize available space, then loss of substance is reduced (space utilization improved), but read performance deteriorates due to increased access time
Solution Approach 1:
The patent performs preliminary organization of write commands in dedicated submission queues, pre-determining which data will be written to which memory chip. This preliminary action ensures that data is distributed across chips in a manner that optimizes both space utilization and future read access patterns, preventing random data division that would increase read access time.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller monitors the state of memory chips and adjusts the distribution of write commands accordingly. This feedback allows the system to maintain optimal space utilization across chips while ensuring that data placement patterns minimize read access time, as the controller can rebalance data distribution based on current chip states and access patterns.
Data Source
AI summary
A memory controller for controlling a plurality of memory chips of a non-volatile memory includes a first core configured to identify a size of a remaining space of a page to be written in a memory chip on which a write operation is to be performed among the plurality of memory chips and fetch a first write command from a first submission queue among a plurality of submission queues included in a host, the first write command being related to data having a size corresponding to that of the remaining space of the page to be written, and a second core configured to control the non-volatile memory to store data related to the fetched first write command in the remaining space of the page to be written.