Memory Controller Arbitration for Parallel Frame Access
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Solution Overview
Problem
Conventional image processing apparatuses face increased costs and deteriorated processing performance due to the need for multiple frame memories and contention between memory write and read operations, particularly in car-mounted displays that require superimposing various images.
Innovation Solution
An image processing apparatus with multiple frame memories, master sections, a memory controller that arbitrates access requests and controls data transfers, allowing parallel access and allocation of banks between video input and output sections, eliminating the need for dedicated frame memories for each input image and graphic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple frame memories are provided for different video input images and graphics, then the ability to display multiple images superimposed is improved, but the device cost increases
Solution Approach 1:
The patent applies universality by making frame memories serve multiple functions: they are shared between video input sections and drawing sections, and can be accessed by multiple master sections simultaneously. The memory controller enables the same frame memory to be used for different purposes (video input buffering, graphics rendering, display output) without requiring dedicated memories for each function, thereby reducing overall device cost while maintaining the ability to display multiple superimposed images.
Solution Approach 2:
The patent merges previously separate frame memories into a shared resource pool. Instead of having dedicated frame memories for each video input section and drawing section, the system combines them into common frame memories that are accessed through a memory controller. This consolidation reduces the total number of frame memories needed while maintaining all required functionalities through controlled parallel access.
2Device complexity
If each memory has a double buffering region and uses a general single port memory, then memory structure is simplified, but processing performance deteriorates due to contention between write and read operations
Solution Approach 1:
The patent applies segmentation by dividing the frame memory into multiple banks (first bank and second bank). This bank structure allows simultaneous read and write operations to occur in parallel within the same memory, eliminating the performance bottleneck of single-port memories while maintaining the simplicity of a unified memory structure. The memory controller manages which bank is accessed for reading and which for writing.
Solution Approach 2:
The patent implements dynamic operation by enabling the memory to switch between different access modes: single-port mode for simple operations and dual-port mode for high-performance operations requiring simultaneous read and write. The system dynamically selects the appropriate access mode based on the operational requirements, optimizing both structure simplicity and processing performance as needed.
3Productivity
If a memory controller section arbitrates between access requests and controls parallel access, then processing performance is improved, but device complexity increases
Solution Approach 1:
The patent introduces a memory controller as an intermediary component that manages access requests from multiple master sections. Rather than having complex point-to-point control logic in each master section, the memory controller centralizes the arbitration and control functions, simplifying the overall system architecture while enabling sophisticated parallel access management. The controller mediates between multiple sources and the frame memory banks, optimizing performance without requiring each master section to be overly complex.
Data Source
AI summary
An image processing device improves processing performance at low cost. The image processing device is provided with a memory controller that divides up and assigns banks accessed by a video inputter, a drawer, and a video outputter to multiple frame memories. The image processing device arbitrates access requests from master units, such as the video inputter, the drawer, and the video outputter, and controls data transmission so that the multiple master units can access both the frame memories in parallel.