Memory Controller Parallel Command Modules for ECC Bottlenecks
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Solution Overview
Problem
Memory devices with nonvolatile semiconductor memories, such as NAND flash memories, face challenges in achieving high-speed operation while maintaining large storage capacity, particularly due to the complexity of storing multiple bits in a single cell, which increases processing time and inefficiencies in error correction techniques.
Innovation Solution
The implementation of a memory device with a controller that includes separate command issuing modules for read and write operations, allowing for parallel processing of data copying and error correction, enabling the memory device to perform direct copying and other operations without waiting for ECC processing to complete, thus optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored in one cell to increase storage capacity, then storage capacity is improved, but processing time increases and operation speed deteriorates
Solution Approach 1:
The controller is divided into multiple independent command issuing modules (first command issuing module for read commands, second command issuing module for write commands, third command issuing module for erase commands). Each module can operate independently and simultaneously, enabling parallel processing of different operations. This segmentation allows the system to perform multiple operations at the same time, improving overall operation speed while maintaining the ability to store multiple bits per cell for high storage capacity.
2Reliability
If error correction processing is performed sequentially, then data reliability is improved, but processing time increases and productivity deteriorates
Solution Approach 1:
The error correction code (ECC) is calculated and prepared in advance during the write operation. When a read operation is needed, the pre-calculated ECC can be immediately applied without waiting for sequential processing. This preliminary preparation of error correction data allows the system to maintain high data reliability while reducing the time required for error correction operations, thereby improving processing efficiency.
Solution Approach 2:
Multiple command issuing modules operate continuously and simultaneously - while one module is performing error correction, another module can be issuing read or write commands. This continuous operation without idle waiting periods maintains productive action throughout the process, improving overall processing efficiency while ensuring data reliability through continuous error correction monitoring and application.
Data Source
AI summary
According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.