Memory Controller Parallel ECC and Decryption for Low Read Latency
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Solution Overview
Problem
The existing DDR memory systems experience latency and performance issues due to the sequential process of error correction and decryption, which impacts system performance during memory reads.
Innovation Solution
A circuit with multiple modes of operation is introduced, allowing for parallel processing of decryption and ECC decoding, switching to serial mode only when an error is detected to correct and re-decrypt the data, and returning to parallel mode once the ECC pipeline is empty, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential error correction and decryption process is used, then data accuracy is ensured, but memory read latency increases and system performance deteriorates
Solution Approach 1:
The patent segments the error correction and decryption processes into separate parallel pipelines. The ECC decode pipeline and decryption pipeline operate independently and simultaneously, allowing both operations to be performed concurrently without interfering with each other, thus reducing overall latency while ensuring data accuracy through dedicated error checking paths
Solution Approach 2:
The patent performs preliminary error checking through ECC decoding before the decryption process completes. By initiating error correction operations in advance and running them in parallel with decryption, the system identifies and corrects errors early in the data retrieval process, preventing rework and reducing total processing time
2Loss of time
If parallel processing of decryption and error checking is implemented, then memory read latency is reduced, but device complexity increases
Solution Approach 1:
The patent merges the error checking and decryption functions into a unified controller architecture with integrated pipelines. By combining these functions in a single controller unit with shared resources and coordinated operation, the system achieves parallel processing without proportionally increasing overall device complexity
Solution Approach 2:
The patent designs the controller with multi-functional components that can perform both error correction and decryption operations. The controller circuit is engineered to handle multiple functions within a single integrated structure, reducing the need for separate dedicated circuits and thereby limiting the increase in device complexity
Data Source
AI summary
A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.