Memory Controller Parallel Error Correction for SCM Latency
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Solution Overview
Problem
Storage class memory (SCM) devices face challenges in maintaining quality of service (QoS) due to longer latency performance compared to DRAM, particularly during error correction and garbage collection, which degrades service quality and increases latency.
Innovation Solution
A memory controller that performs selective and parallel error correction based on error correction options, including a variable error correction circuit and a fixed error correction circuit, to optimize latency and accuracy during data read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on data read from SCM, then data reliability is improved, but latency increases and QoS deteriorates
Solution Approach 1:
The patent implements dynamic error correction by providing multiple error correction options (first option with reference latency and reference error correction level, second option with maximum error correction level) and selectively applying different correction intensities based on data characteristics and system state. This dynamic approach allows the system to adjust error correction strength in real-time, improving reliability when needed while minimizing latency impact when error rates are low.
Solution Approach 2:
The system changes the parameter of error correction level by offering at least two distinct error correction options. The first error correction option includes a reference latency and a reference error correction level, while the second option provides a maximum error correction level. By switching between these parameter settings, the system optimizes the balance between correction thoroughness and processing speed.
2Measurement precision
If comprehensive error correction is performed, then error correction accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent applies partial error correction by providing a first error correction option with a reference error correction level that may be lower than the maximum available correction level. This partial correction approach is sufficient for many data types and system states, achieving adequate error correction accuracy without the full processing overhead of maximum correction, thus improving processing speed while maintaining acceptable reliability.
3Reliability
If error correction level is increased, then data accuracy is improved, but system resource consumption increases
Solution Approach 1:
The system dynamically adjusts error correction intensity by selecting between multiple error correction options based on data characteristics, error rates, and system state. This dynamic adaptation ensures that high error correction levels (which consume more resources) are applied only when necessary, while lower correction levels are used during normal operation, optimizing the balance between data accuracy and resource consumption.
Data Source
AI summary
A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.