Memory Controller Parallel Parity Generation for Data Reliability
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Solution Overview
Problem
Current memory systems lack effective methods for ensuring data reliability and improving write performance, particularly in ensuring the integrity and accuracy of data stored in nonvolatile memory devices.
Innovation Solution
A controller is introduced that generates a parallel parity using end-to-end and internal parities, which includes error correction mechanisms to validate data integrity and perform chip kill operations, ensuring reliable data storage and rapid write performance by correcting errors and generating parity chunks for data chunks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-parity methods are used for data storage, then device complexity is reduced, but data reliability deteriorates
Solution Approach 1:
The patent segments the parity protection mechanism into two distinct layers: end-to-end parity for cross-die error correction and internal parity for intra-die error correction. This segmentation allows each parity type to specialize in specific error scenarios, improving overall data reliability while maintaining manageable controller complexity through modular error handling
Solution Approach 2:
The patent implements a nested parity structure where internal parity chunks are embedded within data chunks, and end-to-end parity is applied across multiple data chunks. This nested approach enables hierarchical error correction where internal parity handles fine-grained errors and end-to-end parity handles broader error patterns, achieving enhanced reliability without proportionally increasing complexity
2Reliability
If comprehensive error correction mechanisms are implemented, then data reliability is improved, but write performance deteriorates
Solution Approach 1:
The patent performs preliminary error correction by applying internal parity generation and verification during the write operation preparation phase. The integrity checker validates data before programming occurs, preventing erroneous data from being written to memory. This preliminary action reduces the need for costly read-retry cycles later, thereby maintaining write performance while ensuring data integrity
Solution Approach 2:
The patent introduces an integrity checker as an intermediary component between the internal encoder and the memory device. This intermediary validates data integrity using end-to-end parity before programming, acting as a gatekeeper that prevents corrupted data from being written. This mediation ensures high data integrity while maintaining efficient write operations by avoiding unnecessary re-programming cycles
3Reliability
If end-to-end parity is added to all data, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent segments end-to-end parity generation into manageable chunks that are processed in parallel. By dividing the data into multiple data chunks and generating end-to-end parity for each chunk independently, the system achieves better utilization of processing resources and reduces overall parity generation time while maintaining comprehensive error correction capability
Solution Approach 2:
The patent applies end-to-end parity selectively rather than uniformly to all data. The integrity checker determines whether end-to-end parity verification is necessary based on the specific data characteristics and error risk assessment. This partial application approach reduces unnecessary processing time while maintaining error correction capability where it is most needed
Data Source
AI summary
A controller for controlling a memory device may include: an end-to-end decoder suitable for correcting an error in the unit user data and the corresponding end-to-end parity; an internal encoder suitable for generating a data chunk by adding a first internal parity to the source word which includes the unit user data and the end-to-end parity from the end-to-end decoder and buffering the source word into a buffer; an integrity checker suitable for determining whether an error is included in the source word, by using the end-to-end parity from the end-to-end decoder; and a parallel parity generator suitable for receiving the source word from the buffer according to a result of the determination, and completing a parallel parity based on a predetermined number of source words received, wherein the internal encoder is further suitable for generating a parity chunk by adding a second internal parity to the completed parallel parity.