Memory Controller Wear Leveling via Parallel Data Transfer
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Solution Overview
Problem
Existing memory management techniques, such as wear leveling in non-volatile memory devices, are time-consuming due to sequential data transfer processes, which can slow down memory operations and reduce efficiency, especially when performed as background operations.
Innovation Solution
Concurrent data transfer from a source row to a target row during parallel activation of both rows, allowing data to be sensed and written simultaneously, thereby reducing the memory management cycle time and improving wear leveling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential data transfer process is used for wear leveling, then data integrity is maintained, but memory management time is excessive
Solution Approach 1:
The patent applies preliminary action by pre-charging the target row before data transfer begins. This preparation step allows the target row to be ready to receive data immediately when the transfer starts, eliminating setup delays during the actual data movement process and reducing overall memory management time.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the data transfer operation with the activation of the target row. Instead of completing one operation before starting the next, the system maintains continuous productive activity by performing data transfer concurrently with row activation, thereby reducing total cycle time while maintaining data integrity.
2Productivity
If parallel activation of source and target rows is implemented, then wear leveling speed is improved, but risk of data interference increases
Solution Approach 1:
The patent applies segmentation by dividing the data transfer process into distinct phases: pre-charging the target row, transferring data from the source row, and completing the transfer. This segmentation allows parallel operations to occur in a controlled manner, maintaining data integrity while improving speed by overlapping non-conflicting operations.
Solution Approach 2:
The patent uses the word line and bit line structures as intermediaries to manage data flow between source and target rows. These intermediary pathways enable controlled data transfer and simultaneous row activation without direct interference, as the intermediary lines manage the timing and routing of data signals.
Data Source
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AI summary
An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.