Memory Controller Parallel Verify Operation for Programming Speed
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in programming speed due to the need for multiple verify operations with different voltages for various program states, which increases operation time and complexity.
Innovation Solution
A memory device and operating method that utilize a control logic to simultaneously perform verify operations by applying bit line voltages of different voltage levels to memory cells, allowing for faster programming by determining the appropriate bit line voltage based on threshold voltage differences between target program states and verify voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple verify operations with different voltages are performed for various program states, then programming accuracy is improved, but programming speed deteriorates
Solution Approach 1:
The patent combines multiple verify operations into a single unified verify operation by applying different voltage levels to different bit lines simultaneously. Instead of performing separate verify operations for different program states, the invention merges them into one operation where bit lines are assigned different voltage levels (e.g., first voltage level for first program state, second voltage level for second program state) to enable concurrent verification of multiple states.
Solution Approach 2:
The patent introduces a new dimension of differentiation by applying voltage levels along the bit line dimension rather than performing sequential operations. By assigning different voltage levels to different bit lines within the same verify operation cycle, the invention transforms the temporal sequence of verify operations into a spatial parallel structure, enabling simultaneous verification of multiple program states.
2Reliability
If multiple verify operations with different voltages are performed for various program states, then verification completeness is improved, but operation complexity increases
Solution Approach 1:
The patent makes the verify operation universal by designing a single verify operation structure that can handle multiple program states simultaneously. The same verify operation circuit and control logic are used for all program states, with the distinction being the voltage level applied to different bit lines. This multi-functional approach eliminates the need for separate dedicated verify operations for each program state, reducing operational complexity while maintaining verification completeness.
Solution Approach 2:
The patent changes the voltage level parameter of the bit lines to differentiate between various program states during a single verify operation. Instead of creating different operation structures for different states, the invention varies the voltage level parameter (e.g., 0V for first state, Vpp for second state) across different bit lines, allowing the same operation framework to verify multiple states with different threshold voltage requirements.
3Ease of operation
If sequential verify operations are performed for different program states, then operation simplicity is maintained, but programming time increases
Solution Approach 1:
The patent ensures continuity of useful action by performing verify operations for multiple program states without interruption or sequential waiting. All verify operations for different program states occur simultaneously within the same time cycle, eliminating the idle time and sequential execution delays that would otherwise occur between separate verify operations for different states.
Data Source
AI summary
A memory controller controlling a semiconductor memory device, the memory controller may comprises a host interface configured to receive a write request, from a host, to store data in the semiconductor memory device, a processor configured to generate a program command according to a type of the write request, a memory interface configured to provide the program command to the semiconductor memory device, wherein the type of the write request includes a first type write request and a second type write request, and wherein the first type write request requires faster write completion response than the second type write request.