Memory Controller Parallel Write Erase Logic

The memory controller performs preliminary actions by pre-mapping logical addresses to physical erasing units across multiple memory units before actual data writing occurs. This preparation enables parallel processing during the writing phase, where multiple erasing units can be simultaneously written to or erased, thereby increasing data writing speed without compromising data integrity.

The memory storage device is segmented into multiple memory units (first memory unit and second memory unit), each containing multiple physical erasing units. This segmentation allows independent parallel operations on different erasing units simultaneously. The logical address space is also segmented and mapped across these physical units, enabling the system to bypass the transmission interface speed limitation by performing multiple write operations in parallel.

The system merges data writing operations with data erasing operations into a single coordinated process. When data is written to a new physical erasing unit, the system simultaneously erases the old physical erasing unit that previously held the data. This combining of write and erase operations into parallel simultaneous actions increases overall throughput without significantly complicating control, as the memory controller manages both operations through integrated logic.

The system ensures continuous useful action by eliminating idle time between write and erase operations. While one erasing unit is being written to, another erasing unit is simultaneously being erased in preparation for future writes. This continuous parallel processing maximizes throughput by ensuring that erasing operations never wait for writing operations to complete, and vice versa, maintaining constant productive activity across all memory units.