Memory Controller Parallel Write Partitioning
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Solution Overview
Problem
In memory systems based on the client/server model, particularly UFS, the existing technologies face limitations in data write efficiency due to restrictive write size requirements and sequential access to NAND flash memory, which hinders parallel operations and degrades response capabilities.
Innovation Solution
A memory device with a controller that divides data write operations into page-sized units, allowing for parallel data transfer and write operations across multiple logical units, thereby optimizing data write efficiency and response capability by determining the size and position of write data parts in response to host requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data write operations are performed with restrictive write size requirements and sequential access, then write operations are simple to control, but data write efficiency is limited and response capability is degraded
Solution Approach 1:
The controller divides incoming data write requests into multiple page-sized units, enabling parallel write operations to different pages of the NAND flash memory. This segmentation allows the system to bypass the limitation of sequential access while maintaining compatibility with the memory's page-based write architecture, thereby improving data write efficiency without requiring fundamental changes to the memory device.
Solution Approach 2:
The controller dynamically determines the size and position of write data parts based on the host's write request and the current state of the memory device. This dynamic adaptation allows the system to optimize write operations in real-time, switching between sequential and parallel access patterns as needed, thus improving response capability while maintaining control simplicity.
2Reliability
If sequential access to NAND flash memory is used, then access control is simplified, but parallel operations are hindered and response capability is degraded
Solution Approach 1:
The controller acts as an intermediary between the host device and the NAND flash memory, translating high-level write requests into optimized page-level operations. It manages the complexity of parallel access control internally while presenting a simplified interface to the host, thus improving response capability without burdening the host with complex access control logic.
Solution Approach 2:
The controller changes the access pattern parameter from sequential to parallel by adjusting how write operations are scheduled and executed. It modifies internal timing and addressing parameters to enable simultaneous access to multiple pages, thereby improving response capability while maintaining the same external interface and control mechanism.
3Productivity
If data is written without aligning to page boundaries, then data transfer flexibility is improved, but partial page writes occur and write efficiency is reduced
Solution Approach 1:
The controller performs preliminary alignment of write data to page boundaries before initiating the write operation. It pre-processes the data buffer, padding or trimming data as necessary to ensure proper alignment, thereby preventing partial page writes and maintaining high write efficiency. This preliminary action occurs transparently in the controller, preserving flexibility for the host application.
Data Source
AI summary
According to one embodiment, a memory device includes a nonvolatile memory in which data write or data read is executed in units of a plurality of cells, and a controller configured to control the memory and to manage a memory space of the memory by dividing the memory space into a plurality of partitions.