Memory Controller Parity Allocation for 3-Bit NAND Error Correction
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Solution Overview
Problem
The increasing probability of errors in NAND flash memory due to miniaturization and super multi-level cell techniques leads to higher parity data requirements, increasing memory size and costs, while maintaining current error correction capabilities is challenging without increasing parity data, resulting in inefficient error correction and increased error probabilities.
Innovation Solution
A memory system with a memory controller that allocates data across multiple pages with varying parity sizes, using error correction coding to improve error correction capability and reading speed by optimizing data allocation and parity distribution across pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amount of parity data is increased to maintain data validity after error correction, then error correction capability is improved, but memory size required for retaining parity data increases, causing cost increase
Solution Approach 1:
The patent divides parity data into multiple segments (first parity data and second parity data) with different sizes, where the first parity data corresponds to a first page and the second parity data corresponds to a second page. This segmentation allows different error correction capabilities for different pages without requiring uniform increase in total parity data across all pages, thereby improving error correction where needed while controlling overall memory usage.
Solution Approach 2:
The patent applies different parity data sizes to different pages based on their specific error correction needs. The first page receives first parity data with a first size, while the second page receives second parity data with a second size. This local differentiation allows optimization of error correction capability for each page individually rather than uniformly increasing parity data across the entire memory, thus improving reliability locally without proportionally increasing total memory size.
2Quantity of substance
If the amount of parity data is not increased to prevent cost increase, then memory size is optimized, but error correction capability deteriorates and probability of error remaining increases
Solution Approach 1:
The patent implements partial error correction action by providing different amounts of parity data for different pages based on their specific requirements. Instead of applying uniform excessive parity data to all pages (which would waste memory), the system applies sufficient parity data only where needed (first page with first parity data, second page with second parity data), achieving adequate error correction capability without unnecessary memory consumption.
3Device complexity
If traditional error correction methods are used, then implementation is simple, but reading speed decreases due to inefficient error correction processes
Solution Approach 1:
The patent segments the error correction process into multiple stages corresponding to different pages. The error correction is performed separately for the first page using first parity data and for the second page using second parity data. This segmentation allows parallel or independent processing of different pages, improving reading speed by avoiding sequential processing of all pages together, while maintaining manageable complexity through modular error correction operations.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.