Memory Controller Parity Buffering for Write Latency
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Solution Overview
Problem
The time required to write data to a memory device is delayed due to the time needed for calculating parity, and existing systems face inefficiencies in managing parity stored in memory devices.
Innovation Solution
A memory system and controller that set super memory blocks, calculate parity using XOR operations, store it in a parity buffer, and write it to separate parity blocks when the buffer is full, while maintaining a parity map and valid parity table to efficiently manage and restore data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity is calculated before writing data to memory device, then data integrity is ensured, but writing time is delayed
Solution Approach 1:
The patent pre-calculates parity values and stores them in a parity buffer before actual data writing is needed. This preliminary action allows the parity to be ready when data writing occurs, eliminating the need to calculate parity during the critical data write path and thus reducing writing time while maintaining data integrity.
Solution Approach 2:
The patent introduces a parity buffer as an intermediary component that decouples the parity calculation process from the data writing process. The buffer acts as a mediator that holds pre-calculated parity values, allowing data to be written without waiting for parity calculation, thereby resolving the time delay while ensuring data integrity through the use of pre-computed parity.
2Productivity
If parity is stored in separate parity blocks, then parity management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into separate functional blocks: data blocks for storing user data and dedicated parity blocks for storing parity information. This segmentation allows independent management of data and parity, improving parity management efficiency by enabling targeted access and operations on parity blocks without affecting data blocks, while the increased structural complexity is justified by the operational benefits.
Solution Approach 2:
The patent creates a multi-functional memory structure where certain memory blocks can serve dual purposes: functioning as data blocks during normal operation and as parity blocks when needed for error correction. This universality improves management efficiency by allowing flexible allocation and reuse of memory resources, while the underlying unified memory architecture helps manage complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the delay in writing data by calculating parity in parallel and efficiently manages parity, enhancing overall memory device performance and data integrity.
Implementation Method 1
The value of I-th bit, where I is a natural number of the first parity may be a value obtained by performing an XOR operation on the I-th bit values of respective sub-data of the plurality of sub-data.
Data Source
AI summary
Embodiments relate to a memory system, a memory controller, and a method of operating the same, wherein a plurality of super memory blocks are set, a parity for data stored in the first super memory block is calculated, the calculated parity is stored in a parity buffer, and the parity stored in the parity buffer is written to one of a plurality of parity blocks included in a memory device. Thus, it is possible to solve the problem that the time for writing data to the memory device is delayed due to the time for calculating the parity, and to efficiently manage the parities stored in the memory device.