Memory Controller Parity Allocation for Non-Volatile Storage
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Solution Overview
Problem
Current memory systems face challenges in efficiently processing and storing data, leading to operational complexity and performance degradation, which affects the durability and performance of non-volatile memory devices.
Innovation Solution
A memory system that generates parity entries for multiple data entries and determines the location for storing these parity entries, using a controller to allocate memory blocks based on program-erase cycles and update map data to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in non-volatile memory devices, then data storage capacity is improved, but operational complexity and performance degradation occur
Solution Approach 1:
The memory system is divided into multiple memory channels, each handling independent data operations. The controller segments data processing tasks across multiple channels, allowing parallel operation and reducing the operational complexity of managing large storage capacity.
2Quantity of substance
If data is stored in non-volatile memory devices, then data storage capacity is improved, but performance degradation occurs
Solution Approach 1:
Multiple memory channels operate in parallel to handle data read/write operations simultaneously. This segmentation of storage operations across channels maintains high performance while providing large aggregate storage capacity.
Solution Approach 2:
The system performs preliminary data processing and parity generation before data is written to memory channels. This preliminary action prepares data in advance, reducing the time required during actual write operations and maintaining performance despite large storage capacity.
3Reliability
If parity entries are generated for multiple data entries, then data reliability is improved, but processing complexity increases
Solution Approach 1:
Parity generation is segmented into individual operations for each memory channel. Each channel generates its own parity entries independently, distributing the processing complexity across multiple units rather than requiring complex centralized processing.
Solution Approach 2:
Each memory channel autonomously generates and manages its own parity entries without requiring complex coordination with other channels. This self-service approach to parity generation improves data reliability while keeping processing complexity manageable at the channel level.
Data Source
AI summary
A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks for storing or outputting plural data entries and a first parity entry associated with the plural data entries. The controller a second parity entry based on a part of the plural data entries, an updated data entry which renews the part of the plural data entries, and the first parity entry, in response to an update event regarding the part of the plural data entries, allocate, for storing the second parity entry, a first memory block having least program-erase cycles among the plurality of memory blocks, allocate, for storing the updated data entry, a second memory block storing the first parity entry, and control the memory device to program the updated data entry and the second parity entry in the first memory block and the second memory block.