Memory Controller Parity Distribution for Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in data error correction when chip failures occur, particularly when data is written in a distributed manner across multiple non-volatile memory chips, as the error correction capability is overwhelmed, leading to data loss and increased latency due to the need to identify and correct errors across multiple chips.
Innovation Solution
The memory system employs a distributed writing method where data frames include both user data and error correction bits, with additional XOR parity written on a separate chip, allowing for parallel error correction across multiple chips without identifying failed chips, thereby reducing latency and preventing circuit scale increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written in a distributed manner across multiple memory chips to reduce latency, then write speed is improved, but error correction capability deteriorates when chip failures occur
Solution Approach 1:
The data frame is segmented and distributed across multiple memory chips (first through fourth chips), with each chip storing a portion of the data. This segmentation enables parallel write operations to improve speed while the patent compensates for the distributed architecture's error correction weakness by implementing a systematic parity distribution scheme where each chip also stores parity information for other chips, ensuring that failure of any single chip does not compromise overall data recoverability
Solution Approach 2:
The patent implements prior cushioning by pre-distributing parity information across multiple chips before any failure occurs. Each memory chip stores not only its own data portion but also parity information that can reconstruct data from other chips. This preparatory arrangement ensures that when a chip failure occurs, the system can immediately recover data using the pre-positioned parity information without experiencing the latency penalty of identifying and locating failed chips
2Reliability
If traditional error correction methods are used after chip failure, then data recovery is attempted, but latency increases due to the need to identify failed chips
Solution Approach 1:
The patent performs preliminary action by pre-distributing parity information across all memory chips during the write operation, before any failure can occur. This means that when a chip fails, the system does not need to perform time-consuming identification and location of failed chips, as the parity information is already positioned and ready for immediate use in data reconstruction, thereby maintaining low latency while ensuring reliable data recovery
Solution Approach 2:
The patent inverts the traditional error correction approach by having each memory chip store parity information for other chips rather than relying on a centralized error correction mechanism. Instead of identifying failed chips and then locating parity information, the system is designed so that any chip can immediately provide parity for any other chip, reversing the traditional flow and eliminating the need for failure identification latency
3Reliability
If XOR parity is written on a separate chip to enable error correction, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing each memory chip to serve multiple functions: each chip stores both its own data portion and parity information for other chips. This multi-functional design eliminates the need for dedicated separate parity storage chips or complex centralized error correction circuits, as any chip can potentially provide parity for any other chip, thereby improving data reliability while maintaining relatively simple device architecture
Data Source
AI summary
A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N−1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.