Memory Controller Parity Verification for Host Memory Buffer Security
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Solution Overview
Problem
The existing memory systems using host memory buffers (HMBs) face security vulnerabilities and data integrity issues due to improper access and caching of data, which can lead to data leakage and corruption.
Innovation Solution
A memory system that generates and verifies parity using a key value for data cached in the HMB, ensuring secure storage and integrity by using a unique key value for each enabling period and managing cache destinations based on data priority and type to prevent unauthorized access and corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is cached in the host memory buffer (HMB) to speed up processing, then processing speed is improved, but security vulnerability and data integrity issues worsen
Solution Approach 1:
The patent introduces parity data as an intermediary element between the cached data and the verification process. The parity data is generated by XORing the data bits and is stored alongside the cached data in the HMB. This intermediary parity information enables integrity verification without requiring the entire data to be re-read from non-volatile memory, thus maintaining both speed and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the controller continuously verifies cached data against the stored parity data. When data is read from the HMB, the controller recalculates the parity from the data bits and compares it with the stored parity. This feedback loop detects any corruption or unauthorized modification of cached data, ensuring integrity while allowing fast access to the HMB.
2Productivity
If HMB is used for temporary storage to improve performance, then productivity is improved, but unauthorized access and data leakage risks increase
Solution Approach 1:
The parity data serves as an intermediary security layer that mediates between the fast HMB storage and the security requirements. It allows the system to benefit from HMB's high-speed access while maintaining security through the verification mechanism, preventing unauthorized access without sacrificing productivity.
Solution Approach 2:
The patent applies preliminary action by generating and storing parity data before any data is cached in the HMB. This preliminary parity information is prepared in advance and stored alongside the data, enabling rapid verification without requiring additional real-time computation during data access operations, thus maintaining high productivity while ensuring security.
3Reliability
If parity verification is performed on cached data to ensure integrity, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent uses parity data as a simple intermediary that provides integrity verification through a straightforward XOR-based mechanism. This approach avoids complex cryptographic operations or multi-step verification processes, maintaining device simplicity while ensuring data integrity through the parity check mechanism.
Solution Approach 2:
The patent changes the parameter of data representation by adding a single parity bit (or word) to the data structure. This parameter change enables integrity verification without fundamentally altering the data storage or access mechanisms, thus avoiding increased device complexity while improving reliability.
Data Source
AI summary
According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.