Memory Controller Parity Reconstruction for Multibit Failure Recovery
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Solution Overview
Problem
Existing memory systems face inefficiencies in data recovery and read operations, particularly when dealing with multibit failures, as they often require direct access to the affected memory chip, which can lead to prolonged operation times and interruptions in data retrieval.
Innovation Solution
The implementation of a memory system using an error correction technique like chipkill, where parity is generated and stored across multiple memory chips, allowing data from a selected memory chip to be reconstructed from unselected chips without direct access, enabling parallel operations and faster read times even during error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct access to the affected memory chip is used for data recovery, then data can be read from the selected memory chip, but the read operation time is prolonged and interruptions occur
Solution Approach 1:
The system performs preliminary actions by generating and storing parity data from multiple memory chips before any failure occurs. When a multibit failure is detected in a selected memory chip, the controller can immediately reconstruct the failed data by reading the pre-stored parity data from unselected memory chips, eliminating the need for time-consuming direct access to the failed chip and enabling continuous parallel operations.
2Productivity
If a memory chip is occupied by another on-going operation or is inaccessible, then the memory chip cannot be accessed for data retrieval, but using parity from other chips allows data reconstruction without accessing the occupied chip
Solution Approach 1:
The system introduces parity data as an intermediary element that mediates between the occupied/inaccessible memory chip and the data retrieval operation. Instead of directly accessing the occupied chip, the controller uses the pre-stored parity data from other memory chips to reconstruct the required data, effectively bypassing the accessibility issue and enabling parallel operations without interference.
3Reliability
If error correction techniques are implemented to handle multibit failures, then data recovery is improved, but the complexity of the memory system increases
Solution Approach 1:
The system applies segmentation by dividing the memory system into multiple independent memory chips, each storing a portion of the overall data set along with parity information. This segmentation allows the failure of one chip to be isolated and corrected without affecting the entire system, as the controller can reconstruct failed data using parity from other segmented chips, thereby improving reliability while maintaining manageable system complexity through modular architecture.
Data Source
AI summary
The technology disclosed in this patent document can be implemented in embodiments to provide a memory system capable of improving a read operation, using an error correction technique (e.g., chipkill) that recovers data in correcting a data failure including a multibit failure, and an operation method of the memory system. The disclosed read operations based on recovery can be used for retrieving data from a memory chip by reconstructing the same data from other memory chips without accessing the memory chip and can be applied in various memory systems.