Memory Controller Parity Recovery for NAND Flash Data Integrity

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Solution Overview

Problem

NAND flash memory devices experience performance degradation and wear out over time due to disturbance and retention issues, leading to a lack of free blocks for data updates and potential data corruption, which existing RAID technologies do not adequately address.

Innovation Solution

A memory system with a memory controller and array that utilizes parity information to recover and refresh user data, employing heating repair operations for unavailable memory devices and maintaining a control table with refresh and repair lists to manage data integrity and accessibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If NAND flash memory is used to improve performance, then storage speed and accessibility are improved, but the memory device wears out after writing lots of data causing no free block to update data or read corrupt data

Engineering Contradiction:
Improvestorage speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The storage system is segmented into multiple memory devices (first, second, third, and fourth memory devices) that store different types of data (user data and parity data) separately. This segmentation allows the system to maintain high-speed access to user data while using dedicated devices for error correction and recovery, thus preserving both speed and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system prepares recovery capacity in advance by dedicating specific memory devices (third and fourth devices) to store parity information and recoverable data. When data corruption occurs, this pre-prepared cushioning capacity enables immediate recovery without affecting the performance of normal read/write operations, thus maintaining both speed and reliability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If RAID technology is applied to prevent damage from device crash, then data reliability is improved, but performance drops due to disturbance and retention matters in NAND flash

Engineering Contradiction:
Improvedata reliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The RAID system is segmented into specialized devices: user data devices (first and second devices) optimized for performance, and parity/recovery devices (third and fourth devices) optimized for reliability. This segmentation allows parallel operations where user data access does not interfere with parity calculations, maintaining high performance while ensuring data reliability through RAID-like protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller acts as an intermediary that manages the separation between user data operations and parity/recovery operations. It coordinates read/write requests to user data devices independently from parity calculations stored in dedicated devices, eliminating the performance penalty typically associated with RAID by mediating between reliability requirements and speed requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If parity information is stored to recover user data, then data recovery capability is improved, but storage capacity is reduced due to redundant parity data

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Storage capacity is segmented into user data capacity (first and second devices) and parity/recovery capacity (third and fourth devices). This clear segmentation allows the system to maximize user data storage while dedicating a specific portion to parity and recovery functions, making the capacity trade-off explicit and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality requirements are applied locally to different devices: user data devices are optimized for capacity and access speed, while parity devices are optimized for reliability and recovery capability. This local quality differentiation allows the system to achieve high data recovery capability without uniformly reducing the quality or capacity of user data storage areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10545805B2Memory system, reading method thereof and writing method thereof
Publication Date: 2020.01.28 MACRONIX INTERNATIONAL CO LTD
  • US10545805B2 patent drawing
  • US10545805B2 patent drawing
  • US10545805B2 patent drawing

AI summary

A memory system, a reading method and a writing method are provided. The memory system includes a memory controller and a memory array electrically connected to the memory controller. A parity information is stored in the memory array. The memory array includes a plurality of memory devices. The reading method comprises the following steps: A reading command for requesting a user data stored in the memory array is received from a host interface. The user data is recovered according to the parity information when the user data is error at one of the memory devices. The user data, which is recovered, is transferred to the host interface and the user data is refreshed.