Memory Controller Parity Region Allocation
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data integrity due to varying fail bit occurrences across different word-lines, leading to inefficiencies in error correction and reliability, especially near the drain selection line where fail bits are more frequent.
Innovation Solution
A controller for a semiconductor memory device is designed to allocate larger parity-data regions for pages with higher fail bit possibilities and smaller regions for those with lower fail bits, generating more parity-data for pages closer to the drain selection line to enhance error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform parity-data regions are used for all pages, then device complexity is reduced, but error correction capacity is insufficient for pages near the drain selection line
Solution Approach 1:
The patent applies local quality by configuring different parity-data region sizes according to the specific location of each page within the memory array. Pages closer to the drain selection line are assigned larger parity-data regions to address higher fail bit occurrences, while pages farther away use smaller regions. This localized differentiation optimizes error correction capacity where needed without uniformly increasing complexity across the entire device.
2Reliability
If larger parity-data regions are allocated to all pages, then error correction capacity is improved, but storage efficiency decreases
Solution Approach 1:
Instead of uniformly increasing parity-data allocation across all pages, the patent implements local quality by selectively allocating larger parity-data regions only to pages with higher failure probabilities (those near the drain selection line). Pages with lower failure rates maintain smaller parity-data regions, thereby preserving storage efficiency while concentrating error correction resources where they are most needed.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the size of parity-data regions based on the physical location of pages within the memory array. The parity-data region size is varied as a function of distance from the drain selection line, optimizing the balance between error correction capacity and storage efficiency for each specific page location.
3Reliability
If more parity-data is generated for pages near the drain selection line, then fail bit correction is improved, but overall device complexity increases
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through location-based differentiation. A determination is made based on the physical address to identify whether a page is located near the drain selection line, and only then is enhanced parity-data generation applied. This localized approach improves fail bit correction where necessary while avoiding the complexity of uniformly enhancing parity-data management across the entire memory array.
Data Source
AI summary
The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.