Memory Controller Parity Checking for Faster Reliable Writes
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Solution Overview
Problem
Current data path protection technologies in memory systems face challenges in increasing data reliability while reducing operation time during write operations in non-volatile memory devices.
Innovation Solution
A controller is implemented with Error Correction Code (ECC) encoding, Low Density Parity Check (LDPC) encoding, and syndrome check operations to enhance data reliability by adding and correcting parities during data transfer, thereby simplifying the data transfer logic and improving reliability without increasing buffer usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple encoding operations (ECC, LDPC, syndrome check) are performed sequentially to increase data reliability, then data reliability is improved, but operation time increases
Solution Approach 1:
The patent applies preliminary action by performing syndrome check operations before the actual write operation to memory. The controller performs ECC encoding, LDPC encoding, and syndrome check operations on the data before it is written to the memory device. This allows error detection and correction to be prepared in advance, so that during the write operation, the data is already validated and ready for reliable storage, reducing the overall operation time while maintaining high data reliability
Solution Approach 2:
The patent segments the data processing into multiple independent encoding stages: ECC encoding stage, LDPC encoding stage, and syndrome check stage. Each stage processes specific aspects of error correction independently. The controller can manage these segments efficiently and write them to different regions or handle them in parallel where possible, reducing the cumulative time impact of multiple encoding operations
2Reliability
If multiple encoding operations are performed to increase data reliability, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple encoding functions (ECC encoder, LDPC encoder, syndrome check logic) into a single integrated controller unit. Rather than having separate independent devices for each encoding operation, the controller combines these functions and manages them through a unified control architecture. This integration reduces overall system complexity while maintaining the benefits of multiple encoding layers for data reliability
Data Source
AI summary
A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.