Memory Controller Partial Bad Block Table Parallel Access

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Solution Overview

Problem

Existing memory systems face inefficiencies in accessing multiple memory chips in parallel due to variations in the number of good and bad blocks, leading to reduced access efficiency as not all memory chips can be operated simultaneously, especially when bad string units are present.

Innovation Solution

The memory system employs a controller that manages blocks and string units by grouping them logically, using a Partial Bad Block Table (PB table) to identify and exclude bad string units, allowing for parallel access across all memory chips regardless of bad block distribution, and updates this information dynamically based on performance changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory chips are accessed in parallel, then memory access efficiency is improved, but variations in bad block distribution cause some chips to be excluded from parallel access, reducing overall efficiency

Engineering Contradiction:
Improvememory access efficiencyVSAvoidparallel access consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the memory management into two levels: block-level segmentation (traditional) and string unit-level segmentation (innovative). By dividing blocks into string units and further into memory cells, the system can identify and exclude only the specific bad string units rather than entire blocks, enabling finer-grained parallel access control across multiple memory chips.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating each string unit within a block as having potentially different quality characteristics. Instead of uniformly treating all string units in a block as good or bad, the system individually identifies bad string units using the PB table, allowing good string units to remain accessible while excluding only the defective ones from parallel access operations.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If traditional block-level bad block management is used, then management simplicity is maintained, but access efficiency is reduced because entire blocks must be excluded when any string unit is bad

Engineering Contradiction:
Improvemanagement simplicityVSAvoidaccess efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments the bad block management approach from traditional block-level granularity to string unit-level granularity. The PB table stores bad block information with additional fields identifying specific bad string units within each block, enabling the system to manage and exclude only the defective string units rather than entire blocks, thus improving access efficiency while maintaining manageable complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to bad block management by introducing string unit identification within blocks. The PB table structure is extended to include not just block addresses but also string unit indices, creating a two-level addressing scheme that enables precise identification of bad components without sacrificing the overall management framework.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If bad blocks are excluded from parallel access, then error correction reliability is improved, but the number of accessible memory chips is reduced

Engineering Contradiction:
Improveerror correction reliabilityVSAvoidnumber of accessible chips
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the specific bad string units from their parent blocks for exclusion from parallel access. Rather than excluding entire blocks or chips, the system identifies and isolates only the defective string units using the PB table, allowing the remaining good string units in the same blocks to continue participating in parallel access operations on other chips.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by excluding only the necessary portion (bad string units) from parallel access rather than the entire block or chip. This selective exclusion maintains error correction reliability by removing only the defective components while preserving access to the majority of memory resources across all chips.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10289480B2Memory system
Publication Date: 2019.05.14 KIOXIA CORP
  • US10289480B2 patent drawing
  • US10289480B2 patent drawing
  • US10289480B2 patent drawing

AI summary

A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.