Memory Controller Partial Data Verification for Write Reliability

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Solution Overview

Problem

Conventional data writing methods using multi-page programming mode in non-volatile memory modules are less reliable and require extensive verification and backup processes, leading to increased time and resource consumption due to the need for single-page programming mode backup and verification across all physical programming units.

Innovation Solution

A data writing method that utilizes multi-page programming mode for initial data writing, followed by single-page programming mode for specific high-risk data units and subsequent verification, allowing only partial data verification and backup, thereby reducing the overall time and resource requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multi-page programming mode is used for data writing, then writing speed is improved, but data reliability deteriorates

Engineering Contradiction:
Improvewriting speedVSAvoiddata reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies partial action by performing single-page programming mode backup only for specific high-risk physical programming units (those with higher failure probabilities) rather than all units. This selective approach maintains data reliability for critical areas while avoiding the excessive time consumption of universal backup, thus resolving the contradiction between writing speed and data reliability.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If single-page programming mode backup is performed for all data, then data reliability is improved, but writing time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidwriting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by differentiating the treatment of different physical programming units based on their failure probabilities. High-risk units receive single-page programming backup while low-risk units use only multi-page programming mode. This localized quality assurance maintains overall data reliability while significantly reducing total writing time compared to universal backup.

Inventive Principle:
Principle #3Local quality

3Reliability

If verification is performed on all physical programming units, then data integrity is improved, but verification time increases

Engineering Contradiction:
Improvedata integrityVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality to verification by focusing verification efforts on high-risk physical programming units that have higher failure probabilities. Low-risk units are either partially verified or not verified at all. This selective verification strategy maintains data integrity for critical areas while dramatically reducing overall verification time.

Inventive Principle:
Principle #3Local quality

4Reliability

If extensive backup and verification processes are performed, then data reliability is improved, but resource consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidresource consumption
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by performing backup and verification operations only where necessary based on failure probability assessments. Instead of exhaustive backup and verification of all data, the system performs these operations selectively on high-risk physical programming units, thereby maintaining data reliability while reducing resource consumption and improving overall productivity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10936248B2Data writing method with verifying a part of data, memory controlling circuit unit and memory storage device
Publication Date: 2021.03.02 PHISON ELECTRONICS
  • US10936248B2 patent drawing
  • US10936248B2 patent drawing
  • US10936248B2 patent drawing

AI summary

A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.