Memory Controller Pattern Conversion for Forbidden Data Sequences
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Solution Overview
Problem
In densely packed memory devices, data loss occurs due to interference between memory cells, leading to errors that existing technologies struggle to effectively minimize.
Innovation Solution
A memory controller system that includes a pattern transformer and de-transformer, using finite state machines and buffers to convert data between numeral systems, maps alphabet letters, and inserts or restores them to avoid forbidden patterns that cause data loss, ensuring reliable data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are densely packed to increase storage capacity, then storage density is improved, but data loss occurs due to interference between memory cells
Solution Approach 1:
The patent applies preliminary action by transforming the data pattern before writing to memory. The pattern transformer converts input data streams into transformed patterns that avoid forbidden sequences known to cause interference. This preventive transformation is performed before the data is written to densely packed memory cells, thereby preventing data loss due to cell interference while maintaining high storage density.
Solution Approach 2:
The patent changes the parameter representation of data by converting between different numeral systems (e.g., base-3 to base-4 conversion). This parameter transformation allows the same information to be stored in a format that avoids problematic patterns, thus reducing data loss in densely packed memory while preserving storage capacity.
2Reliability
If data patterns are transformed to avoid forbidden patterns, then data reliability is improved, but device complexity increases due to additional transformation components
Solution Approach 1:
The pattern transformer and pattern de-transformer are designed as multi-functional components that handle both base conversion and pattern transformation operations. These universal components can process different data formats and patterns through the same hardware structure, reducing overall device complexity while maintaining data reliability through forbidden pattern avoidance.
Solution Approach 2:
The patent introduces intermediate buffers and state machines as mediators between the data stream and memory. These intermediary components manage the transformation process, temporarily storing data during conversion and coordinating the operations of pattern transformer and de-transformer, thereby simplifying the overall system architecture while ensuring reliable data storage and retrieval.
3Reliability
If base conversion is performed on data streams, then forbidden patterns are avoided, but processing time increases due to conversion operations
Solution Approach 1:
Base conversion and pattern transformation are performed as preliminary operations before data is written to memory. By converting data to the appropriate numeral system and transforming patterns in advance, the system avoids the need for complex real-time conversions during write operations, thereby reducing overall processing time while maintaining forbidden pattern avoidance.
Solution Approach 2:
The pattern transformer and de-transformer operate continuously on data streams, processing multiple data elements in parallel through pipelined operations. This continuous processing maintains high throughput by keeping transformation operations ongoing without idle periods, minimizing the time penalty associated with base conversion while ensuring consistent forbidden pattern avoidance.
Data Source
AI summary
A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.