Memory Controller Urgent Command Pausing Mechanism

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Solution Overview

Problem

Existing storage systems face challenges in reducing data access latency, particularly in complex workload situations where multiple commands from different hosts need to be prioritized and managed efficiently.

Innovation Solution

A memory controller and nonvolatile memory device architecture that includes a scheduler to prioritize commands based on urgency, pausing operations of less urgent commands to perform more urgent ones first, and resuming the paused operations after completing the urgent tasks, along with a queue system to manage and sequence commands accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If commands are processed in sequential order as received, then system operation is simple, but data access latency increases in complex workload situations

Engineering Contradiction:
Improvedata access latencyVSAvoidcommand management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The command queue is segmented into multiple priority levels (e.g., high priority and normal priority queues). The memory controller divides command processing into priority-based segments, allowing urgent commands to be processed separately from routine commands, thereby reducing data access latency for time-sensitive operations without significantly increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The command scheduling system dynamically adjusts processing order based on command priority and current operational state. The memory controller can dynamically switch between processing commands in received order or in priority order, and can pause/resume command operations adaptively, enabling flexible response to varying workload conditions while maintaining manageable complexity.

Inventive Principle:
Principle #15Dynamics

2Speed

If urgent commands interrupt ongoing operations, then data access latency for urgent commands is reduced, but system operation complexity increases

Engineering Contradiction:
Improvecommand processing speedVSAvoidoperation control complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory controller performs preliminary actions by pre-processing command validation and priority assignment before execution. Commands are pre-categorized into priority levels and staged in appropriate queues before actual execution, allowing urgent commands to be quickly identified and processed without requiring complex real-time decision-making during execution, thus improving processing speed while controlling complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A command scheduler acts as an intermediary between command reception and execution. This intermediary component manages the interruption and resumption of operations by coordinating between urgent commands and ongoing operations, absorbing the complexity of interrupt management and presenting a simplified interface to both command sources and execution units.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple hosts send commands simultaneously, then system versatility is improved, but command scheduling complexity increases

Engineering Contradiction:
Improvemulti-host support capabilityVSAvoidcommand scheduling complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory controller implements a universal command queue management system that handles commands from multiple hosts through a unified priority-based scheduling mechanism. The same queue structure and scheduling logic serve all hosts regardless of their identity or command type, enabling multi-host support without proportionally increasing scheduling complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Commands from different hosts are segmented into separate tracking structures while sharing a common priority queue system. Each host's commands are individually identifiable and manageable, yet all commands compete for execution resources through the unified priority mechanism, allowing versatile multi-host support with controlled scheduling complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11989451B2Method of operating a memory controller in which commands are stored in urgent or normal queues based on priority. a nonvolatile memory device including a buffer selector and a storage device thereof
Publication Date: 2024.05.21 SAMSUNG ELECTRONICS CO LTD
  • US11989451B2 patent drawing
  • US11989451B2 patent drawing
  • US11989451B2 patent drawing

AI summary

A method for operating a memory controller, the method including: receiving a first command from a first host; storing the first command in a queue; when the first command has a higher priority than a second command currently being performed, pausing an operation of the second command and performing a read operation of the first command; and continuing the operation of the second command after completion of the read operation of the first command.