Memory Controller Page Buffer Table Data Comparison
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Solution Overview
Problem
Current memory systems face challenges in minimizing power consumption and data toggling during write and read operations due to the need for buffer operations, which are inefficient and consume significant power.
Innovation Solution
A memory system with a controller and memory device that includes a page buffer table (PBT) and scheduler, which compares write or read data to data stored in the PBT, allowing for selective performance of buffer operations based on data similarity, thereby reducing unnecessary data toggling and power consumption by skipping buffer operations when data is unchanged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If buffer operations are performed during write and read operations, then data transmission between memory device and controller is enabled, but power consumption increases and data toggling occurs
Solution Approach 1:
The page buffer table pre-stores data that may be needed for future write or read operations. By having this data prepared in advance in the controller, the system can skip buffer operations when the pre-stored data matches the required data, thereby reducing power consumption while maintaining data transmission capability.
Solution Approach 2:
The patent creates a copy of page buffer data in the page buffer table within the controller. This copy allows the controller to compare and determine whether buffer operations are necessary, avoiding unnecessary data toggling and power consumption while ensuring data can be transmitted when needed.
2Loss of energy
If page buffer table is introduced to compare data and skip buffer operations, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The page buffer table serves multiple functions: it stores data for comparison, acts as a cache for potential read/write operations, and enables the skip buffer operation feature. This multi-functionality justifies the added complexity by providing energy savings across multiple operations without requiring separate dedicated components for each function.
Data Source
AI summary
A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.