Memory Controller Credit Synchronization for Persistence
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Solution Overview
Problem
Current DDR memory protocols fail to support data persistence confirmation, leading to reduced system performance due to the need for PCOMMIT and CLFLUSH instructions that block new write instructions, affecting overall system efficiency.
Innovation Solution
Implementing a system with multiple memory write instruction sets and medium write instruction sets, where credit values are used to manage and synchronize write operations, allowing for accurate persistence confirmation without blocking all write instructions, thus improving parallel processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCOMMIT instruction is used to confirm data persistence by blocking all new write instructions in the memory controller, then data persistence confirmation is achieved, but system performance deteriorates due to blocking of write instructions from all application programs
Solution Approach 1:
The patent divides the memory controller's write instruction handling into multiple independent queues (first queue and second queue). The PCOMMIT instruction operates on write instructions in the first queue without blocking the second queue, allowing other application programs to continue submitting write instructions. This segmentation resolves the contradiction by isolating the persistence confirmation operation to a specific queue while maintaining overall system throughput through parallel processing of the other queue.
2Measurement precision
If all write instructions are blocked to ensure PCOMMIT execution, then persistence confirmation accuracy is improved, but parallel processing efficiency deteriorates
Solution Approach 1:
The patent segments write instructions into different queues based on their persistence requirements. The first queue handles write instructions that need persistence confirmation (subject to PCOMMIT), while the second queue handles write instructions that can proceed without blocking. This allows the system to maintain high parallel processing efficiency by keeping the second queue active while ensuring accuracy for persistence-critical operations in the first queue.
Solution Approach 2:
The patent introduces an intermediary mechanism (the multi-queue structure with credit values) that mediates between the need for accurate persistence confirmation and the need for high parallel processing efficiency. The credit value system acts as a mediator that tracks the state of each queue independently, allowing the PCOMMIT instruction to accurately confirm persistence for the first queue without interfering with the parallel processing of the second queue.
Data Source
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AI summary
This application discloses a non-volatile memory NVM persistence method and a computing device. A credit value is configured for each of at least two memory write instruction sets associated with a memory controller, and a credit value is configured for each of at least two medium write instruction sets associated with a medium controller, where the credit value is changed based on a sending and receiving status and an execution status of a write instruction, and credit values respectively corresponding to a plurality of memory write instruction sets are kept synchronized with credit values respectively corresponding to a plurality of specified medium write instruction sets in the medium controller; and after the credit values of the memory controller and the medium controller are kept synchronized, whether persistence of the write instruction is completed can be accurately found based on the credit values. In addition, setting the plurality of memory write instruction sets can implement local blocking at a granularity of a memory write instruction set during the persistence query, to improve parallel processing efficiency of the memory controller.