Memory Controller PIM Command Scheduling
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Solution Overview
Problem
In von Neumann architecture, the increased speed of processors is limited by the von Neumann bottleneck due to waiting times for data transfer between memory and processor, as memory improvements focus on storing more data in less space rather than enhancing transfer speed, leading to inefficiencies in data access.
Innovation Solution
A memory controller with a first buffer, command generator, and command scheduler that determines the order of memory requests based on whether they correspond to Processing-In-Memory (PIM) or general memory, using an area separating bit to differentiate addresses and optimize command execution order for efficient access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory transfer speed is improved to match processor speed, then processor efficiency is improved, but memory complexity increases
Solution Approach 1:
The memory system is segmented into PIM memory and general memory regions, with the memory controller capable of distinguishing and handling commands for each type separately. This segmentation allows optimized command scheduling for PIM operations while maintaining standard memory operations, thereby improving effective transfer speed without requiring complete memory system redesign
Solution Approach 2:
The command scheduler dynamically adjusts command execution order based on the target memory type. For PIM memory, commands are executed in a different order compared to general memory, allowing the system to adapt its operation mode to match the specific requirements of each memory type and improve overall data access efficiency
2Productivity
If command execution order is optimized for PIM memory, then PIM operation efficiency is improved, but command scheduler complexity increases
Solution Approach 1:
Different command scheduling strategies are applied to different memory types. The command scheduler implements local quality by using specialized scheduling logic only for PIM memory commands while maintaining standard scheduling for general memory, thereby improving PIM operation efficiency without requiring complete redesign of the command scheduling system
Solution Approach 2:
The system changes the parameter of command execution order based on the target memory type. By detecting whether a command targets PIM or general memory, the command scheduler adjusts the execution order parameter accordingly, enabling efficient PIM operations through parameter adjustment rather than structural complexity
3Measurement precision
If memory address differentiation is implemented, then memory access precision is improved, but address field complexity increases
Solution Approach 1:
The address field uses an asymmetric structure with a specific bit (area separating bit) dedicated to indicating memory type. This asymmetric design allows the system to differentiate between PIM and general memory addresses with high precision while maintaining a relatively simple address field structure, as only one bit is added rather than requiring complete address field redesign
Data Source
AI summary
A memory controller includes: a first buffer configured to receive a memory request from a host and store therein the received memory request; a command generator configured to generate a first command corresponding to the memory request, and set a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory; a second buffer configured to store therein a plurality of commands comprising the first command; and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.