Memory Controller PIM Command Reordering
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Solution Overview
Problem
In systems that implement applications like neural networks and IoT, a bottleneck often occurs due to the large amount of data being received and transmitted between semiconductor devices and processors, which existing technologies fail to address effectively by not optimizing the ordering of processing in memory (PIM) commands.
Innovation Solution
A memory controller is designed to identify and reorder PIM commands based on unique ID and ordering information within the data field of write commands, allowing for efficient execution of operations in memory without the need for sequential command ordering, thereby minimizing memory bandwidth loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PIM commands are transmitted in sequential order from host core to memory controller, then memory operations are performed correctly in order, but command transmission time and memory bandwidth are wasted due to sequential processing requirements
Solution Approach 1:
The memory controller performs preliminary reordering of PIM commands before transmission to the memory device. By identifying PIM commands among multiple commands and reordering them based on ordering information in advance, the system ensures correct execution order without requiring sequential transmission, thus reducing command transmission time while maintaining reliability
Solution Approach 2:
The memory controller acts as an intermediary between the host core and memory device. It receives commands from the host core, identifies PIM commands, reorders them based on ordering information, and transmits the reordered commands to the memory device. This intermediary function resolves the contradiction by handling reordering in the middle layer, allowing the host core to generate commands efficiently while ensuring correct execution order at the memory device
2Productivity
If the host core generates commands without synchronization overhead, then command generation efficiency is improved, but command ordering may be incorrect for PIM operations
Solution Approach 1:
The memory controller serves as an intermediary that receives commands generated efficiently by the host core without synchronization overhead. It identifies PIM commands among the received commands and reorders them based on ordering information embedded in the commands, thus ensuring correct ordering without requiring the host core to implement complex synchronization mechanisms
Solution Approach 2:
The host core includes ordering information within the command structure itself, allowing the memory controller to perform self-service reordering without external intervention or synchronization overhead from the host. The memory controller autonomously identifies PIM commands and reorders them based on the embedded ordering information, maintaining both efficiency and reliability
3Productivity
If PIM commands are reordered based on ordering information, then memory bandwidth utilization is optimized, but device complexity increases due to additional identification and reordering logic
Solution Approach 1:
The memory controller integrates multiple functions into a single device: command reception, PIM command identification, ordering information verification, command reordering, and command transmission. By combining these functions in the memory controller, the system optimizes memory bandwidth utilization without requiring separate dedicated hardware components for each function, thus limiting the increase in device complexity
Data Source
AI summary
A memory controller, a method of operating the memory controller, and an electronic device including the memory controller are disclosed. The method of operating a memory controller, comprising receiving, from a host core, a plurality of commands for a memory, identifying, from among the plurality of commands, processing in memory (PIM) commands to execute one or more operations in the memory, verifying ordering information from a data field in each of the PIM commands, and reordering the PIM commands based on the ordering information and transmitting the reordered PIM commands to the memory.