Memory Controller Command Scheduler for PIM Integration
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Solution Overview
Problem
Conventional Processing-in-Memory (PIM) technology in memory devices is limited to specific applications and cannot perform general memory read or write operations during processing operations, leading to performance deterioration in memory systems.
Innovation Solution
A memory controller and device architecture that integrates a request queue, command generator, command scheduler, and processing circuit to manage memory and PIM commands, allowing simultaneous execution of memory operations and processing tasks using a shared bus, eliminating the need for separate interfaces for PIM commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PIM technology is adopted to perform processing operations in memory device, then processing capability is improved, but general memory read and write operations cannot be performed during processing operation, leading to performance deterioration
Solution Approach 1:
The patent segments the command handling into separate queues: a first queue for memory commands and a second queue for PIM commands. This segmentation allows independent management and scheduling of different command types, enabling memory operations to continue during PIM processing without interference, thus resolving the contradiction between processing capability and overall system performance
Solution Approach 2:
The patent implements dynamic command scheduling where the controller can flexibly allocate resources and adjust command execution priorities based on current system state. The scheduler dynamically determines when to execute memory commands versus PIM commands, allowing the system to adaptively balance processing operations with memory access operations to maintain high productivity
2Ease of operation
If separate interfaces are provided for PIM commands, then processing operation control is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal command interface that can handle both memory commands and PIM commands through the same physical interface and state machine. The command decoder is designed to universally decode different command types without requiring separate dedicated interfaces, thereby maintaining ease of operation for processing control while avoiding the complexity increase that would result from separate interfaces
Solution Approach 2:
The patent merges the handling of memory commands and PIM commands into a unified command processing architecture. Both command types share the same command queue structure, decoding logic, and execution framework, which simplifies the overall device structure while maintaining the ability to independently control processing operations through the integrated command scheduling mechanism
Data Source
AI summary
A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.