Memory Controller Scheduling for Concurrent PIM and Memory Requests
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies when processing-in-memory (PIM) requests and conventional memory requests are handled sequentially, leading to performance bottlenecks and overheads during mode transitions.
Innovation Solution
A memory controller system that concurrently issues PIM requests to one group of memory banks and memory requests to idle groups, optimizing performance by interleaving operations and managing mode transitions to minimize overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PIM requests and memory requests are handled sequentially, then the system is simpler to manage, but performance is reduced due to bottlenecks and switching overheads
Solution Approach 1:
The memory banks are divided into multiple groups, with different groups handling PIM requests and memory requests concurrently. This segmentation allows parallel processing of different request types without requiring complex interleaving logic within a single bank group, thus improving performance while managing complexity through spatial division.
Solution Approach 2:
The system transitions from sequential request handling in a single dimension to concurrent handling across multiple dimensions by utilizing different bank groups simultaneously. This dimensional expansion allows PIM requests and memory requests to be processed in parallel, eliminating bottlenecks without proportionally increasing control complexity.
2Adaptability or versatility
If the system switches between PIM mode and non-PIM mode, then it can handle different types of requests, but switching overhead is introduced
Solution Approach 1:
The system performs preliminary actions during idle periods by pre-fetching data, pre-positioning bank groups, and preparing for upcoming request types. This allows mode transitions to occur more quickly since the system is already partially prepared, reducing switching overhead while maintaining flexibility in handling different request types.
Solution Approach 2:
Instead of completely stopping and resetting during mode switches, the system maintains continuous useful action by having different bank groups operate continuously on different request types. This eliminates idle time during transitions and reduces switching overhead while preserving adaptability to handle both PIM and memory requests.
3Productivity
If all memory banks are dedicated to PIM operations, then PIM performance is maximized, but conventional memory requests cannot be processed concurrently
Solution Approach 1:
Memory banks are segmented into multiple groups with different functional specializations. Some bank groups are dedicated to PIM operations to maximize throughput, while other bank groups handle conventional memory requests. This segmentation allows both PIM performance and memory request capability to coexist without resource conflicts.
Solution Approach 2:
The memory system is designed with multi-functionality where bank groups can be dynamically allocated or configured for different purposes. This universality allows the system to maximize PIM performance when needed while simultaneously maintaining the capability to process conventional memory requests, achieving both high throughput and adaptability.
Data Source
AI summary
A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.