Memory Controller Pipeline Synchronization Using Filler Instructions

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Solution Overview

Problem

The significant time gap between the processor and memory controller operations in computing devices, despite the use of cache memories, necessitates further techniques to enhance instruction execution efficiency.

Innovation Solution

The implementation of a mechanism where the processor asserts a dequeue signal to synchronize the execution of instructions between the processor and memory controller pipelines, using filler and null instructions to manage the pipeline execution and reduce power consumption by asserting the signal only once per group of consecutive filler instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processor operates at a faster rate than the memory controller, then the processor execution speed is improved, but the memory controller becomes a bottleneck causing instruction transfer delays

Engineering Contradiction:
Improveprocessor execution speedVSAvoidinstruction transfer time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The memory controller prefetches instructions into the pipeline before they are needed by the processor. The pipeline is pre-loaded with instructions in advance, allowing the processor to execute without waiting for the memory controller to transfer each instruction individually. This preliminary action resolves the speed mismatch by having instructions ready before the processor needs them.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The instruction transfer process is segmented into multiple stages using a pipeline structure. Instead of transferring instructions one at a time sequentially, the system divides the instruction stream into segments that can be transferred and executed in parallel across different pipeline stages, reducing the overall transfer time bottleneck.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the memory controller transfers instructions sequentially one by one, then the transfer process is simple, but the processor waits longer for instructions

Engineering Contradiction:
Improveinstruction transfer processVSAvoidinstruction execution throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The memory controller prefetches instructions into the pipeline before they are needed by the processor. The pipeline is pre-loaded with instructions in advance, allowing the processor to execute without waiting for the memory controller to transfer each instruction individually. This preliminary action resolves the speed mismatch by having instructions ready before the processor needs them.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipeline ensures continuous instruction transfer and execution by maintaining multiple instructions in different stages of processing simultaneously. Once instructions are fetched, they continue through the pipeline stages without interruption, ensuring the processor always has the next instruction ready to execute, eliminating idle wait time.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If the processor waits for instructions to be transferred from memory, then the memory controller can transfer instructions sequentially, but the processor execution is delayed

Engineering Contradiction:
Improvememory controller transfer efficiencyVSAvoidprocessor wait time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The memory controller prefetches instructions into the pipeline before they are needed by the processor. The pipeline is pre-loaded with instructions in advance, allowing the processor to execute without waiting for the memory controller to transfer each instruction individually. This preliminary action resolves the speed mismatch by having instructions ready before the processor needs them.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipeline ensures continuous instruction transfer and execution by maintaining multiple instructions in different stages of processing simultaneously. Once instructions are fetched, they continue through the pipeline stages without interruption, ensuring the processor always has the next instruction ready to execute, eliminating idle wait time.

Inventive Principle:
Principle #20Continuity of useful action

4Productivity

If cache memories are used to keep frequently executed instructions close to the processor, then the effective performance is increased, but additional techniques are still needed to further manage instruction execution

Engineering Contradiction:
Improveeffective performanceVSAvoidinstruction management system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The instruction transfer process is segmented into multiple stages using a pipeline structure. Instead of transferring instructions one at a time sequentially, the system divides the instruction stream into segments that can be transferred and executed in parallel across different pipeline stages, reducing the overall transfer time bottleneck.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory controller prefetches instructions into the pipeline before they are needed by the processor. The pipeline is pre-loaded with instructions in advance, allowing the processor to execute without waiting for the memory controller to transfer each instruction individually. This preliminary action resolves the speed mismatch by having instructions ready before the processor needs them.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8190830B2Method, apparatus, and systems to support execution pipelining in a memory controller
Publication Date: 2012.05.29 INTEL CORP
  • US8190830B2 patent drawing
  • US8190830B2 patent drawing
  • US8190830B2 patent drawing

AI summary

A memory controller may execute instructions instead of sending the instructions to a processor for execution. To maintain synchronization between the memory controller and the processor, the memory controller may queue a null instruction in the memory controller for each non-filler instruction sent to the processor and may send a filler instruction to the processor for each non-null instruction to be executed by the memory controller.