3D IC Memory Controller Placement in Distributed TSV Farms
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Solution Overview
Problem
In three-dimensional integrated circuits (3DICs), achieving reduced footprint and memory access latency simultaneously is challenging due to the complexity of traditional two-dimensional ICs, and centralized TSV farms lead to increased wire-length and thermo mechanical reliability issues.
Innovation Solution
The implementation of distributed through-silicon-via (TSV) farms in 3DICs allows for improved memory controller placement, with options for centralized or distributed schemes to minimize memory access latency by positioning memory controllers adjacent to TSV farms, thereby reducing intra-tier routing complexity and enhancing thermo mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a centralized TSV farm is used to reduce interconnection delays, then wiring distances between electrical components are minimized, but wire-length between memory controller and memory IC increases and routing complexity increases
Solution Approach 1:
The patent divides the single centralized TSV farm into multiple distributed TSV farms positioned at different locations within the semiconductor IC tier. This segmentation allows memory controllers and memory ICs to be placed closer to their respective TSV farms, reducing wire-length while maintaining efficient interconnections through the distributed via structures.
2Loss of time
If memory controller is placed close to memory IC to minimize access latency, then memory access latency is reduced, but footprint increases due to routing around centralized TSV farm
Solution Approach 1:
The patent transitions from a two-dimensional layout with centralized TSV farm to a three-dimensional distributed architecture where multiple TSV farms are positioned at different spatial locations. This dimensional change enables memory controllers and memory ICs to be placed in optimal positions closer to their respective TSV farms, reducing both access latency and routing footprint simultaneously.
3Reliability
If distributed TSV farms are used to improve PPA and reliability, then thermo mechanical reliability improves and routing complexity reduces, but memory controller placement becomes more challenging
Solution Approach 1:
The patent applies local quality by positioning specific TSV farms at strategic locations corresponding to where memory controllers and memory ICs will be placed. Each distributed TSV farm serves a localized region, enabling memory controllers to be placed close to their dedicated TSV farms without requiring complex global routing, thus simplifying placement while maintaining reliability.
4Device complexity
If memory controller is placed away from TSV farm to simplify routing, then routing complexity reduces, but memory access latency increases
Solution Approach 1:
By segmenting the TSV infrastructure into multiple distributed farms rather than one centralized farm, the patent enables memory controllers to be positioned adjacent to their local TSV farms. This segmentation eliminates the need for long-distance routing while maintaining simple local connections, thus reducing both routing complexity and access latency simultaneously.
Data Source
AI summary
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.