Memory Controller Plane-Aware Data Sequencing
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing the programming sequence of data across multiple planes in memory devices, leading to inefficiencies in data storage and retrieval, particularly when addresses correspond to different or the same planes.
Innovation Solution
A memory controller is designed to allocate addresses for M-bit multi-level cell (MLC) blocks and manage the transmission sequence of logical page data based on whether the addresses correspond to the same or different planes, using a data sequence manager to queue and transmit data effectively across interleaving and non-interleaving block groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are programmed sequentially without considering plane allocation, then the control logic is simple, but data storage efficiency deteriorates due to unnecessary programming operations across different planes
Solution Approach 1:
The memory controller pre-determines the transmission sequence of logical page data by checking whether first and second addresses correspond to the same plane before actual data transmission. This preliminary sequencing action prevents unnecessary programming operations and improves data storage efficiency without adding complex runtime control logic
Solution Approach 2:
The system uses the address information itself to determine the transmission sequence. By checking whether addresses correspond to the same plane, the memory controller automatically adjusts the programming sequence without requiring external control signals or complex scheduling algorithms
2Measurement precision
If the transmission sequence is optimized for same-plane addresses, then data retrieval accuracy improves, but the system complexity increases due to conditional sequence determination
Solution Approach 1:
The memory controller applies different transmission sequencing strategies based on the local characteristic of address plane correspondence. When addresses correspond to the same plane, one sequencing method is applied; when they correspond to different planes, another method is applied. This localized optimization ensures data retrieval accuracy without requiring a completely complex system-wide redesign
Solution Approach 2:
The system changes the transmission sequence parameter based on the plane correspondence condition. By dynamically adjusting the sequencing parameter according to whether addresses are in the same plane, the system achieves accurate data retrieval while keeping the control mechanism simple and conditional
3Productivity
If logical page data are transmitted in a fixed sequence, then the control mechanism is simple, but data storage efficiency deteriorates when addresses correspond to different planes
Solution Approach 1:
The transmission sequence is made dynamic rather than fixed. The memory controller adjusts the sequencing based on the plane correspondence of addresses, allowing the system to adapt to different data storage scenarios. This dynamic adjustment improves data storage efficiency while maintaining relatively simple control through conditional logic
Data Source
AI summary
There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.