Memory Controller Polar Coding With CRC for Multi-Bit Cell Reads
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Solution Overview
Problem
Multi-bit memory cells in semiconductor devices face reliability issues due to overlapping threshold voltage distributions, leading to increased read failure rates and data errors as the number of bits programmed in each cell increases, causing charge loss and characteristic deterioration over time.
Innovation Solution
A controller and semiconductor memory system employing a method that includes dividing messages into sub-messages, adding cyclic redundancy check (CRC) parity messages, and performing polar encoding and decoding operations to enhance data reading precision, utilizing CRC decoding and successive cancellation list decoding schemes to correct errors and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits programmed in each memory cell increases to achieve high integration, then storage capacity is improved, but reliability of stored data decreases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the data transmission process into multiple stages with intermediate CRC checks. The original message is divided into sub-messages, each processed separately with its own CRC parity message. This segmentation allows error detection and correction at multiple points, preventing error propagation and maintaining data reliability even when storing multi-bit data in each cell.
Solution Approach 2:
The patent applies preliminary error protection by adding CRC parity messages to sub-messages before polar encoding. This preliminary action creates a robust encoded message structure that can withstand the threshold voltage distribution overlaps inherent in high-density MLC storage, ensuring data reliability is maintained from the outset.
2Measurement precision
If CRC parity message length is increased to improve error detection capability, then data accuracy is improved, but message length and storage requirements increase
Solution Approach 1:
Instead of adding one large CRC parity message to the entire message, the patent segments the message into sub-messages and adds smaller CRC parity messages to each segment. This approach provides distributed error detection coverage, maintaining high data accuracy while keeping the total overhead lower than a single comprehensive CRC would require.
Solution Approach 2:
The patent applies CRC protection selectively to sub-messages rather than treating the entire message as one unit. This partial action approach provides sufficient error detection capability for each segment without the excessive overhead of protecting the entire message with a single large CRC, achieving an optimal balance between accuracy and efficiency.
Data Source
AI summary
An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.